ST7MC1K2 datasheet(282/371 Pages) STMICROELECTRONICS

282 / 371 page

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Caution:

1: The PWM mode is selected via the 00[5:0] bits in the MPHST register, the OE[5:0] bits in

the MPAR register and the OS2 and OS0 bits in the MCRB register as shown in Table 134:

PWM mode when SR = 1 on page 269.

Caution:

2: When driving motors with three independent pairs of complementary PWM signals

(PCN = 1), disabling the deadtime generator (DTE = 0) causes the deadtime to be null: high

and low side signals are exactly complemented.

It is therefore recommended not to disable the deadtime generator (it may damage the

power stage), unless deadtimes are inserted externally.

Polarity register (MPOL)

Warning:

OP[5:0] bits in the MPOL register must be configured as

required by the application before enabling the MCO[5:0]

outputs with the MOE bit in the MCRA register.

MPOL

Reset value: 0011 1111 (3Fh)

654

ZVD

REO

OP[5:0]

R/W

Write once only

Table 156.

MPOL register description

Bit

Name

Function

7ZVD

Z vs D edge polarity

0: Zero-crossing and End of Demagnetization have opposite edges

1: Zero-crossing and End of Demagnetization have same edge

6REO

Read on High or Low channel bit(1)

0: Read the BEMF signal on High channels

1: Read on Low channels

This bit always has to be configured whatever the sampling method.

5:0

OP[5:0]

Output channel polarity(2)

These bits are used together with the OO[5:0] bits in the MPHST register to control

the output channels (see Table 157).

0: Output channel is Active Low

1: Output channel is Active High

Write-once bits; once write-accessed these bits cannot be rewritten unless the processor is reset (see

‘Caution: Access to write-once bits’ on page 280).

Table 157.

Output channel state control

OP[5:0] bit

OO[5:0] bit

MCO[5:0] pin

1 (Off)

0 (PWM possible)

0 (Off)

1 (PWM possible)

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