ST72321R6-Auto datasheet(52/243 Pages) STMICROELECTRONICS

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Interrupts

ST72321xx-Auto

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Doc ID 13829 Rev 1

flag is set in the peripheral status registers and if the corresponding enable bit is set in

the peripheral control register.

The general sequence for clearing an interrupt is based on an access to the status

Note:

The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be

serviced) will therefore be lost if the clear sequence is executed.

7.3

Interrupts and low power modes

All interrupts allow the processor to exit the Wait low power mode. On the contrary, only

external and other specified interrupts allow the processor to exit from the Halt modes (see

column “Exit from Halt/Active Halt” in Table 20: Interrupt mapping). When several pending

interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt

with “exit from Halt mode” capability and it is selected through the same decision process

shown in Figure 18.

Note:

If an interrupt that is not able to exit from Halt mode is pending with the highest priority when

exiting Halt mode, this interrupt is serviced after the first one serviced.

7.4

Concurrent and nested management

The following Figure 19 and Figure 20 show two different interrupt management modes. The

first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the

nested mode in Figure 20. The interrupt hardware priority is given in this order from the

lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for

each interrupt.

Warning:

A stack overflow may occur without notifying the software of

the failure.

Figure 19.

Concurrent interrupt management

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

SOFTWARE

3/0

11 / 10

RIM

IT3

PRIORITY

LEVEL

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