ST72321R6-Auto datasheet(37/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

Supply, reset and clock management

Doc ID 13829 Rev 1

37/243

Supply, reset and clock management

6.1

Introduction

The device includes a range of utility features for securing the application in critical

situations (for example in case of a power brown-out), and reducing the number of external

components. An overview is shown in Figure 9.

For more details, refer to the dedicated parametric section.

6.2

Main features

●

Optional PLL for multiplying the frequency by 2 (not to be used with internal RC

oscillator)

●

Reset Sequence Manager (RSM)

●

Multi-oscillator Clock Management (MO)

–

5 crystal/ceramic resonator oscillators

–

1 internal RC oscillator

●

System Integrity Management (SI)

–

Main supply low voltage detection (LVD)

–

Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply or the EVD pin

Figure 9.

Clock, reset and supply block diagram

LOW VOLTAGE

DETECTOR

(LVD)

fOSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

VSS

EVD

VDD

RESET SEQUENCE

MANAGER

(RSM)

OSC2

MAIN CLOCK

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REAL-TIME

CLOCK (MCC/RTC)

AVD AVD AVD LVD

WDG

fOSC

(option)

fCPU

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