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ST72321R6-Auto 数据表(PDF) 27 Page - STMicroelectronics |
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ST72321R6-Auto 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 243 page  ST72321xx-Auto Register and memory map Doc ID 13829 Rev 1 27/243 000Ch 000Dh 000Eh Port E PEDR PEDDR PEOR Port E Data Register Port E Data Direction Register Port E Option Register 00h(1) 00h 00h R/W R/W(2) R/W(2) 000Fh 0010h 0011h Port F PFDR PFDDR PFOR Port F Data Register Port F Data Direction Register Port F Option Register 00h(1) 00h 00h R/W R/W R/W 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh I2C I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register 00h 00h 00h 00h 00h 00h 00h R/W Read Only Read Only R/W R/W R/W R/W 001Fh 0020h Reserved Area (2 bytes) 0021h 0022h 0023h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control/Status Register xxh 0xh 00h R/W R/W R/W 0024h 0025h 0026h 0027h ITC ISPR0 ISPR1 ISPR2 ISPR3 Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 FFh FFh FFh FFh R/W R/W R/W R/W 0028h EICR External Interrupt Control Register 00h R/W 0029h FLASH FCSR Flash Control/Status Register 00h R/W 002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W 002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W 002Ch 002Dh MCC MCCSR MCCBCR Main Clock Control / Status Register Main Clock Controller: Beep Control Register 00h 00h R/W R/W 002Eh to 0030h Reserved Area (3 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh TIMER A TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register 00h 00h xxxx x0xx b xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Table 4. Hardware register map (continued) Address Block Register label Register name Reset status Remarks |
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