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ST72321xx-Auto

Interrupts

Doc ID 13829 Rev 1

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7.6.2

External interrupt control register (EICR)

EICR

Reset value: 0000 0000 (00h)

543

IS1[1:0]

IPB

IS2[1:0]

IPA

TLIS

TLIE

Table 21.

EICR register description

Bit

Name

Function

7:6

IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following

external interrupts:

- ei2 (port B3..0) (see Table 22)

- ei3 (port B7..4) (see Table 23)

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1

(level 3).

5IPB

Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can

be set and cleared by software only when I1 and I0 of the CC register are both set

to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

4:3

IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following

external interrupts:

- ei0 (port A3..0) (see Table 24)

- ei1 (port F2..0) (see Table 25)

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1

(level 3).

2IPA

Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can

be set and cleared by software only when I1 and I0 of the CC register are both set

to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

1TLIS

TLI sensitivity

This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by

software only when TLIE bit is cleared.

0: Falling edge

1: Rising edge

0TLIE

TLI enable

This bit allows to enable or disable the TLI capability on the dedicated pin. It is set

and cleared by software.

0: TLI disabled

1: TLI enabled

Note: A parasitic interrupt can be generated when clearing the TLIE bit.

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