ST72321R9-Auto datasheet(41/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

Supply, reset and clock management

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Figure 12.

RESET sequence phases

6.5.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up

resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Section 19.9: Control pin

characteristics on page 207for more details.

A RESET signal originating from an external source must have a duration of at least

th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and

therefore the MCU can enter reset state even in Halt mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in Section 19:

Electrical characteristics.

If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 13),

the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see

long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the

device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

6.5.3

External power-on RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

ensure by means of an external reset circuit that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC frequency (see Section 19.3: Operating

conditions on page 188).

A proper reset signal for a slow rising VDD supply can generally be provided by an external

RC network connected to the RESET pin.

6.5.4

Internal low voltage detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

●

Power-on RESET

●

Voltage drop RESET

The device RESET pin acts as an output that is pulled low when VDD <VIT+ (rising edge) or

VDD <VIT- (falling edge) as shown in Figure 13.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

RESET

ACTIVE PHASE

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

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