ST72321R9-Auto datasheet(40/243 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST72321xx-Auto

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Doc ID 13829 Rev 1

6.5

Reset sequence manager (RSM)

6.5.1

Introduction

The reset sequence manager includes three RESET sources as shown in Figure 11:

●

External RESET source pulse

●

Internal LVD RESET (low voltage detection)

●

Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic RESET sequence consists of three phases as shown in Figure 12:

●

Active phase depending on the RESET source

●

256 or 4096 CPU clock cycle delay (selected by option byte)

●

RESET vector fetch

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay

should be selected by option byte to correspond to the stabilization time of the external

oscillator used in the application (see Section 21.1.1: Flash configuration on page 223).

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11.

Reset block diagram

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

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