STM8L151C4 datasheet(16/142 Pages) STMICROELECTRONICS

16 / 142 page

Functional overview

STM8L151x4/6, STM8L152x4/6

16/142

DocID15962 Rev 15

3.2

Central processing unit STM8

3.2.1

Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard

architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

•

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

•

8-bit accumulator

•

24-bit program counter - 16 Mbyte linear memory space

•

16-bit stack pointer - access to a 64 Kbyte level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

•

20 addressing modes

•

Indexed indirect addressing mode for lookup tables located anywhere in the address

space

•

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

•

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2

Interrupt controller

The medium-density STM8L151x4/6 and STM8L152x4/6 feature a nested vectored

interrupt controller:

•

Nested interrupts with 3 software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 40 external interrupt sources on 11 vectors

•

Trap and reset interrupts

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