eZ80F91 datasheet(11/30 Pages) ZILOG

11 / 30 page

PS026102-1207

Pin Description

Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP

Product Specification

Input/Output Connector

Figure 3 on page 8 displays the pin layout of the 60-pin I/O connector (JP2) of the Zdots.

However, the eZ80® Development Platform features a 50-pin connector. The Zdots is

designed to interface pin 60 of its JP2 connector to pin 50 of the eZ80 development plat-

form’s JP2 connector so that pins 1–10 of the Zdots overlap the edge of the eZ80 develop-

ment platform. Table 2 on page 8 describes the pins.

GND

VSS/Ground (0 V).

Bidirectional

INSTRD

Output

BUSACK

Output

BUSREQ

PU 2 k

Ω

Input

*Notes

1. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy

timing requirements for the CPU.

2. All unused inputs must be pulled to either VDD or GND, depending on their inactive levels, to reduce power

consumption and to reduce noise sensitivity.

3. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

Table 1. Zdots Peripheral Bus Connector Pin Identification* (Continued)

Pin No Symbol

Pull

Up/Down*

Signal Direction Comments

eZ80F91 数据表(PDF) 11 Page - Zilog, Inc.