PS026102-1207

Onboard Component Description

Product Specification

14

going into High-Z mode, that is, after the end of the eZ80F91 Read access to Flash, it

takes 8.8 ns+25 ns = 33.8 ns before Flash stops driving the data bus. At this point, the

eZ80F91 device is already well into the next bus cycle.

Consider the next cycle to be Memory Write. During the Memory Write cycle, data (out-

put) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write pulse is

asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns from the rising

devices drive the common Data Bus—the eZ80F91 device and Flash. In turn, data that is

being written during the Write operation might be corrupted. The part used to isolate a

slow Flash data bus from a fast eZ80F91 bus has 5.5 ns turn-off time, which reduces 25 ns

26.3 ns, as described in the following equation:

Data being written is not corrupted because the Write pulse is not yet asserted.

Figure 4. Bus Contention without the Zdots Fast Buffer Feature

Time of contention

+

()

6.8 ns

=

=

Clock

-CS0

F91 Data

Bus

-RD

Data IN

Data OUT

-WR

-CS1

FLash

Data Bus

Bus contention

T6

Tod

T3

T4