PS026102-1207

Pin Description

Product Specification

11

57

HALT_SLP

Output, Active

Low

A Low on this pin indicates that the CPU enters

either HALT or SLEEP mode because of

execution of either a HALT or SLP instruction.

58

NMI

PU 10 k

Input, Active

Low

The NMI input is a higher priority input than the

maskable interrupts. It is always recognized at

the end of an instruction, regardless of the state

of the interrupt enable control bits. This input

includes a Schmitt-trigger to allow RC rise times.

This external NMI signal is combined with an

internal NMI signal generated from the WDT

block before being connected to the NMI input of

the CPU.

59

3.3 V supply input pin.

60

Reserved

NC

Reserved—No Connection.

*Notes

1. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy

timing requirements for the CPU.

consumption and to reduce noise sensitivity.

3. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

Table 2. Zdots Input/Output Connector Pin Identification* (Continued)

Pin No

Symbol

Pull

Up/Down

Signal

Direction

Comments