CS5532-AS datasheet(45/52 Pages) CIRRUS

45 / 52 page

CS5531/32/33/34

DS289PP5

2.12. Getting Started

This A/D converter has several features. From a

software programmer’s prospective, what should

be done first? To begin, a 4.9152 MHz or 4.096

MHz crystal takes approximately 20 ms to start. To

accommodate for this, it is recommended that a

software delay of approximately 20 ms start the

processor’s ADC initialization code. Next, since

the CS5531/32/33/34 do not provide a power-on-

reset function, the user must first initialize the ADC

to a known state. This is accomplished by resetting

the ADC’s serial port with the Serial Port Initializa-

tion sequence. This sequence resets the serial port

to the command mode and is accomplished by

transmitting 15 SYNC1 command bytes (0xFF

hexadecimal), followed by one SYNC0 command

(0xFE hexadecimal). Once the serial port of the

ADC is in the command mode, the user must reset

all the internal logic by performing a system reset

sequence (see 2.3.2 System Reset Sequence). The

next action is to initialize the voltage reference

mode. The voltage reference select (VRS) bit in the

configuration register must be set based upon the

magnitude of the reference voltage between the

VREF+ and the VREF- pins.

After this, the channel-setup registers (CSRs) should

be initialized, as these registers determine how cali-

brations and conversions will be performed. Once

the CSRs are initialized, the user has three options in

calibrating the ADC: 1) don’t calibrate and use the

default settings; 2) perform self or system calibra-

tions; or 3) upload previously saved calibration re-

sults to the offset and gain registers. At this point,

the ADC is ready to perform conversions.

2.13. PCB Layout

For optimal performance, the CS5531/32/33/34

should be placed entirely over an analog ground

plane. All grounded pins on the ADC, including the

DGND pin, should be connected to the analog

ground plane that runs beneath the chip. In a split-

plane system, place the analog-digital plane split

immediately adjacent to the digital portion of the

chip.

Note:

See the CDB5531/32/33/34 data sheet for

suggested layout details and Applications

Note 18 for more detailed layout guidelines.

Before layout, please call for our Free

Schematic Review Service.

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