M95M01-R datasheet(19/51 Pages) STMICROELECTRONICS

19 / 51 page

DocID13264 Rev 14

19/51

M95M01-DF M95M01-R

Instructions

6.3

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction is used to read the Status Register. The

Status Register may be read at any time, even while a Write or Write Status Register cycle is

in progress. When one of these cycles is in progress, it is recommended to check the Write

In Progress (WIP) bit before sending a new instruction to the device. It is also possible to

read the Status Register continuously, as shown in Figure 10.

Figure 10. Read Status Register (RDSR) sequence

The status and control bits of the Status Register are as follows:

6.3.1

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such

cycle is in progress.

6.3.2

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write

Enable Latch is reset, and no Write or Write Status Register instruction is accepted.

The WEL bit is returned to its reset state by the following events:

•

Power-up

•

Write Disable (WRDI) instruction completion

•

Write Status Register (WRSR) instruction completion

•

Write (WRITE) instruction completion

6.3.3

BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be

software-protected against Write instructions. These bits are written with the Write Status

to 1, the relevant memory area (as defined in Table 2) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

M95M01-R 数据表(PDF) 19 Page - STMicroelectronics

M95M01-R 数据表(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

数据表下载