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M95010-R 数据表(PDF) 9 Page - STMicroelectronics

部件名 M95010-R
功能描述  Compatible with SPI bus serial interface
PDF  46 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95010-R 数据表(HTML) 9 Page - STMicroelectronics

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M950x0-W M950x0-R M950x0-DF
Signal description
45
2.6
Write Protect (W)
This input signal controls whether the memory is write protected. When Write Protect (W) is
held low, writes to the memory are disabled, but other operations remain enabled.
Write Protect (W) must either be driven high or low, but must not be left floating.
2.7
VSS ground
VSS is the reference for the VCC supply voltage.
2.8
Supply voltage (VCC)
2.8.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 9: Operating
conditions (M950x0-W), Table 10: Operating conditions (M950x0-R) and Table 11:
Operating conditions (M95040-DF, device grade 6)). This voltage must remain stable and
valid until the end of the transmission of the instruction and, for a Write instruction, until the
completion of the internal write cycle (tW).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS
package pins.
2.8.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal reset threshold voltage (this threshold is defined in Table 9: Operating
conditions (M950x0-W), Table 10: Operating conditions (M950x0-R) and Table 11:
Operating conditions (M95040-DF, device grade 6) as VRES).
When VCC passes over the POR threshold, the device is reset and is in the following state:
Standby Power mode
Deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
Status register value:
Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When the device is in the above state, it must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 9:
Operating conditions (M950x0-W), Table 10: Operating conditions (M950x0-R) and
Table 11: Operating conditions (M95040-DF, device grade 6).



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