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M95010-R 数据表(PDF) 35 Page - STMicroelectronics |
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M95010-R 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 46 page ![]() DocID6512 Rev 13 35/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters 45 Table 18. AC characteristics (M950x0-W, device grade 6)(1) Test conditions specified in Table 9 and Table 12 Symbol Alt. Parameter VCC = 2.5 to 5.5 V (2) VCC = 4.5 to 5.5 V Unit Min. Max. Min. Max. fC fSCK Clock frequency D.C. 10 D.C. 20 MHz tSLCH tCSS1 S active setup time 30 - 15 - ns tSHCH tCSS2 S not active setup time 30 - 15 - ns tSHSL tCS S deselect time 40 - 20 - ns tCHSH tCSH S active hold time 30 - 15 - ns tCHSL -S not active hold time 30 - 15 - ns tCH(3) tCLH Clock high time 40 - 20 - ns tCL(3) tCLL Clock low time 40 - 20 - ns tCLCH(4) tRC Clock rise time - 2 - 2 µs tCHCL(4) tFC Clock fall time - 2 - 2 µs tDVCH tDSU Data in setup time 10 - 5 - ns tCHDX tDH Data in hold time 10 - 10 - ns tHHCH - Clock low hold time after HOLD not active 30 - 15 - ns tHLCH - Clock low hold time after HOLD active 30 - 15 - ns tCLHL - Clock low set-up time before HOLD active 0 - 0 - ns tCLHH - Clock low set-up time before HOLD not active 0 - 0 ns tSHQZ(4) tDIS Output disable time - 40 - 20 ns tCLQV(5) tV Clock low to output valid - 40 - 20 ns tCLQX tHO Output hold time 0 - 0 - ns tQLQH(4) tRO Output rise time - 40 - 20 ns tQHQL(4) tFO Output fall time - 40 - 20 ns tHHQV tLZ HOLD high to output valid - 40 - 20 ns tHLQZ(4) tHZ HOLD low to output high-Z - 40 - 20 ns tW tWC Write time - 5 - 5 ms 1. The timing values described in this table are recommended for new designs. 2. Only for devices identified by process letter K. 3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 4. Characterized only, not tested in production. 5. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU. |
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