PC87415VCG datasheet(19/42 Pages) NSC

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70 Functional Description

The Enhanced PCI-IDE controller interfaces up to four IDE

devices directly onto the PCI bus The controller has 4 major

blocks

PCI Interface

Data Buffers

IDE Interface

DMA Controller

71 PCI INTERFACE

711 Commands

The device acts as either a target or a master on the PCI

bus The following PCI commands are recognized by this

device when acting as a target

IO Read

IO Write

Configuration Read

Configuration Write

When this device is a master it generates the following PCI

commands

IO Read

IO Write

Memory Read

Memory Write

All the IO cycles are non-bursting (target or as a master)

Memory Reads and Writes are all burst capable

712 Termination

7121 Target Abort in Target Mode

When the device is operating as a target (the IDE channel

operating in PIO mode) it can generate a target abort under

3 conditions These conditions are as follows

Condition 1 During the address phase a reserved or un-

supported combination on the command inputs

has been detected

Condition 2 During an IO write or read cycle an illegal

combination has been detected on the byte en-

able inputs and the 2 least significant address

lines

Condition 3 During a configuration write or read cycle the 2

least significant address lines have been non-

zero This means the configuration cycle ad-

dress is not double word aligned

Conditions 1 through 3 cause the target-abort bit to be set in

the Status Register (bit 11)

7122 Retry in Target Mode

When the device is a PCI target a WATCHDOGTM timer is

provided to prevent the device from holding the cycle for

more than 32 PCI clocks This timer is enabled through the

Control Register bit 10 If the timer expires a retry is gener-

ated on the PCI bus

7123 Target Abort in Master Mode

When the device is operating as a master (the IDE channel

operating in DMA mode) and the target device issues a tar-

get abort the master cycle will be terminated and the PCI

Status register updated indicating that the master was termi-

nated with a target abort

7124 Retry in Master Mode

When the device is doing a master cycle and the target

responds with a retry the cycle is terminated by de-assert-

ing FRAME

and no data is transferred The device then

tries to continue to do the terminated cycle until successful

7125 Disconnect in Master Mode

When the device is doing a master burst cycle and the tar-

get issues a disconnect command the master cycle termi-

nates the burst cycle by de-asserting FRAME

The device

then continues to transfer the remainder of the burst cycle

by asserting FRAME

again and tries to do another burst

cycle

7126 Master Abort in Master Mode

When the device is operating as a master and the target

doesn’t respond with DEVSEL

by the end of the 6th PCI

clock the master cycle is terminated and a master abort is

signaled by writing into the PCI Status register indicating

that the master cycle was terminated

72 DATA BUFFERS

721 Write Posting

The device provides 4 levels of write posting (16 bytes) per

channel If the buffer is not full the TRDY

signal is re-

turned to the PCI bus 1 clock after DEVSEL

is asserted

during a write operation This provides additional perform-

ance during transfers to the IDE devices Writes to the data

port are only posted Writes to the command or control

block by-pass the posting buffer If the buffer is not empty

and the CPU tries to either access the command or control

port of the current channel in PIO mode the access is held

off until the write buffers of the current channel are flushed

out to the IDE bus and then the command or control port

access is processed using the by-pass mode If the channel

is in DMA mode then the access to the non data port will go

through at a higher priority than the buffered write access

722 Prefetch

The device provides 4 levels of prefetch buffers (16 bytes)

used for both channels Reads to the command or control

block will by-pass the prefetch buffer If the buffer is not

empty and the CPU tries to either access the command or

control port of the current channel in PIO mode the access

is held off until the prefetch buffers of the current channel

are filled and then the command or control port access is

processed using the by-pass mode If the channel is in DMA

mode the access to the non data port will go through even

though there is data in the prefetch buffer

723 Two Channel Buffer Protocol

The device could respond to accesses to another channel

while the buffer of the current channel is being filled or is

full Accesses to the 2 channels are interleaved giving each

channel equal access Interleaving is done on a cycle by

cycle basis If only one channel is being accessed then that

IDE channel is given the full IDE bus bandwidth

73 IDE INTERFACE

The device interfaces IDE drives onto the PCI bus It inter-

cepts IO commands intended for the IDE drives and then

emulates the IDE bus cycles to the drive interface at higher

speeds (eg mode 4) The IO port addresses monitored

are either the legacy addresses or a PCI mapped IO ad-

dresses The IDE port definition is shown in Table I as de-

fined in the ATA interface specification

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