PC87415VCG datasheet(12/42 Pages) NSC

12 / 42 page

50 Configuration Registers (Continued)

Reg

Description

(HEX)

40 – 42

CONTROL REGISTER

(Continued)

Bit 12 0 e All accesses mapped to Base Address Register 10 and 14 bypass the data buffers

1 e IDE device accesses (Control Register bit 14e0) to offset 0 of the base address window

Bit 13 0 e All accesses mapped to Base Address Register 18 and 1C bypass the data buffers

1 e IDE device accesses (Control Register bit 15e0) to offset 0 of the base address window

Bit 14 0 e IDE device mapped to base address window registers 10 and 14

1 e Non-IDE device mapped to base address window registers 10 and 14

Bit 15 0 e IDE device mapped to base address window registers 18 and 1C

1 e Non-IDE device mapped to base address window registers 18 and 1C

Bit 16 0 e Channel 1 prefetch buffer disabled

1 e Channel 1 prefetch buffer enabled

Bit 17 0 e Channel 2 prefetch buffer disabled

1 e Channel 2 prefetch buffer enabled

Bit 18 0 e Resetidle State

1 e IDE

PWR has power onoff function

Bit 19 Reserved

Bit 29 0 e Channel 1 drive 1 IORDY handshaking for flow control

1 e Channel 1 drive 1 DMARQDMACK handshaking for flow control

Bit 21 0 e Channel 1 drive 2 IORDY handshaking for flow control

1 e Channel 1 drive 2 DMARQDMACK handshaking for flow control

Bit 22 0 e Channel 2 drive 1 IORDY handshaking for flow control

1 e Channel 2 drive 1 DMARQDMACK handshaking for flow control

Bit 23 0 e Channel 2 drive 2 IORDY handshaking for flow control

1 e Channel 2 drive 2 DMARQDMACK handshaking for flow control

WRITE BUFFER STATUS

This status information is used for power management Before the software

attempts to turn off power to the IDE drives it must ensure that the write buffer is empty

Bit 0 e 0 Channel 1 write buffer empty

1 Channel 1 write buffer not empty

Bit 1 e 0 Channel 2 write buffer empty

1 Channel 2 write buffer not empty

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