Reg

RW

Description

(HEX)

08

R

REV ID

01h

09

RW

PROGRAMMING INTERFACE (PIF)

Bit 0 This bit determines what addresses channel 1 responds to The default value is the sampled value of the

LEGACY

pin (sampled on the rising edge of RST )

0 Channel 1 responds to addresses 1F0 – 1F7 and 3F6 Base registers 0 and 1 (10h – 17h) are not used

legacy mode

1 Channel 1 responds to addresses programmed in base register 0 and 1native mode

Bit 1 Always 1 Channel 1 has programmable selection of modes Bit 0 determines which mode (default) This

bit is read only

Bit 2 This bit determines what addresses channel 2 responds to The default value is the sampled value of the

LEGACY

pin (sampled on the rising edge of RST )

0 Channel 2 responds to addresses 170 – 177 and 376 Base registers 2 and 3 (18h – 1Fh) are not used

legacy mode

1 Channel 2 responds to addresses programmed in base register 2 and 3native mode

Bit 3 Always 1 Channel 2 has programmable selection of modes Bit 2 determines which mode (default) This

bit is read only

Bit 4 – 6 Reserved

Bit 7 Always 1 Indicating that the device supports Master IDE

0A

R

SUB-CLASS CODE

01h (IDE controller)

0B

R

CLASS CODE

01h (Mass Storage controller)

0C

Not used

0D

RW

LATENCY TIMER

This register specifies in units of PCI bus clocks the value of the 8 most significant bits of an

11-bit Latency Timer for this device when the internal DMA controller is used and the device is a bus master

0E

R

HEADER TYPE

00h

0F

R

BIST

00h

10 – 13

RW

BASE ADDRESS REGISTER 0 (BAR0)

Used for channel 1 datacommand block accesses if channel 1 is

programmed to be in native mode The device decodes 8 bytes of address space for datacommand block

accesses This register is always readwrite regardless of the setting of the NativeLegacy bit in the PIF

Bit 0 always 1

Bit 1 always 0

Bit 2 always 0

14 – 17

RW

BASE ADDRESS REGISTER 1 (BAR1)

Used for channel 1 control block access if channel 1 is programmed to

be in native mode The device decodes 4 bytes of address space for control block accesses This register is

always readwrite regardless of the setting of the NativeLegacy bit in the PIF

Bit 0 always 1

Bit 1 always 0

18 – 1B

RW

BASE ADDRESS REGISTER 2 (BAR2)

Used for channel 2 datacommand block accesses if channel 2 is

programmed to be in native mode The device decodes 8 bytes of address space for datacommand block

accesses This register is always readwrite regardless of the setting of the NativeLegacy bit in the PIF

Bit 0 always 1

Bit 1 always 0

Bit 2 always 0

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