PC87415VCG datasheet(39/42 Pages) NSC

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90 Application Information

91 POWER CONTROL FOR IDE DRIVES

The IDE

PWR pin may be programmed ON or OFF using

bits in the CONTROL REGISTER to allow external transis-

tors to switch power to the IDE power connectors and ca-

bles This feature is useful or ‘‘Green-PC’s’’ and notebook

computers which need to minimize power consumption

At power on as the power supply rises to 5V the IDE

PWR

pin assumes a default logic 1 state After reset the default

value of the control register is 00000000h meaning that you

have to set bit 18 e 1 to define the pin to be operating

under IDE

PWR ONOFF control using bit 3 This will re-

sult in power to the IDE peripheral being turned on after

power up but even as bit 18 is changed froma0toa1 due

to the reversed control polarity used by bit 3 the output

level of this pin will remain at a logic 1 In order to ‘’turn-off’’

the VCC supply to the IDE connectors it is necessary to

program bit 3 to a 1 which sets the output level of the pin to

a logic 0 To turn the VCC supply to the IDE connectors

‘‘back-on’’ set bit 3 to a 0 which will in turn set the output pin

to a logic 1

The table below shows the various bit settings and resulting

output level for the operation of IDE

PWR pin at different

instances in time t

TLF12497 – 36

Comment

Bit 18

0111

Bit 1

After bit 18 is set to a 1 bit 1

becomes a don’t-care

Bit 2

0000

Bit 2 is always set to a 0

Bit 3

0010

Bit 3 used to turn ON and

OFF the VCC control to the

IDE connectors

Mode

Default Value at

Set pin as correct

Set bit 3 e 1 to

Set bit 3 e 0to

power up reset

mode to control

turn IDE

PWR to

turn IDE

PWR to

output pin IDE

logic 0 to set VCC

logic 1 to set VCC

PWR

OFF to IDE

ON to IDE

connectors

92 NATIVE MODE INTERRUPT SUPPORT

The PC87415 can be configured in either legacy mode or

native mode In Legacy mode it routes its interrupts to the

ISA Bus (‘‘IRQ14’’ for Channel 1 and ‘‘IRQ15’’ for Channel

The PC87415 can be set up to power-up and function in

Native Mode by following the procedure outlined below

1 The PC87425 ‘‘DA2’’ IO pin (pin

63) must be pulled

high through a 10 kX resistor The state of the ‘‘DA2’’

input (LEGACY ) upon ‘‘RESET’’ transitioning high will

be loaded into the PCI Configuration Space Register

(Programming Interface Register PIF) The pull-up Re-

sistor on pin ‘‘DA2’’ will cause a logic ‘‘1’’ to be pro-

grammed into bits 0 and 2 of the PIF register thus con-

figuring the PC87415 to be in Native Mode and respond

to accesses in Base Address Register 0 and 1 for Chan-

nel 1 and BAR 2 and 3 for Channel 2

2 The circuit board should route the PC87415 interrupt to

the PCI Bus INTA

The BIOS or system must be able to

route the PCI INTA

input to an appropriate IRQ vector

3 The BIOS must be able to program the PC87415 PCI

Configuration Space ‘‘Base Address Registers 0 – 3 and

4’’

Given the above steps the PC87415 will be able to operate

in 16-bit PIO Mode 0 In order to access the higher perform-

ance possible in the PC87415 the BIOS or Driver must be

able to access the PCI Configuration Space above 3FH

The Control and Timing registers allow the driver or BIOS to

program the PC87415 in higher performance PIO modes

and use full 32-bit PCI accesses and the internal FIFO’s of

the device Lastly the driver must allow accessing through

the PC87415 PCI Configuration Base Address Register

to enable the DMA capabilities of the chip (same as Legacy

Mode Driver)

The PC87415 and the drivers supplied with it fully support

legacy mode The Windows 95 and Windows NT drivers

also support native mode operation

Level vs Edge Sensitive Interrupts

To be in conformance with the PCI specification the PC

motherboard chipsets should be able to handle ‘‘Level Sen-

sitive Interrupts’’ However some older chipsets do not cor

rectly handle Level Sensitive Interrupts particularly in the

instance where the PCI Interrupt pin (INTA ) may be as-

serted and several interrupts are pending via this pin

For those older chipsets which do not correctly handle level

sensitive interrupts the system designer needs to use an

external logic solution such as a GAL programmable logic

device to guarantee generating an edge for each Interrupt

that is pending The GAL should monitor all the interrupts

that are tied to a singular PCI Interrupt pin and the PC87415

INTA

output The GAL also monitors the PC87415 INTA

output and generates its own version of INTA

to the PCI

bus

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