PC87415VCG datasheet(2/42 Pages) NSC

2 / 42 page

Table of Contents

10 GENERAL DESCRIPTION

20 FEATURES

30 SYSTEM DIAGRAM

40 PIN DESCRIPTION

41 PCI Interface

42 IDE Interface

43 Power Control

44 Power and Ground

45 Pinout

50 CONFIGURATION REGISTERS

60 BUS MASTER IDE CONTROL AND STATUS

REGISTERS

70 FUNCTIONAL DESCRIPTION

71 PCI Interface

711 Commands

712 Termination

7121 Target Abort in Target Mode

7122 Retry in Target Mode

7123 Target Abort in Master Mode

7124 Retry in Master Mode

7125 Disconnect in Master Mode

7126 Master Abort in Master Mode

72 Data Buffers

721 Write Posting

722 Prefetch

723 Two Channel Buffer Protocol

73 IDE Interface

731 IDE Protocol

7311 PIO Single Sector Reads

7312 PIO Block Mode Reads

7313 PIO Single Sector Writes

7314 PIO Block Mode Writes

7315 DMA Mode

732 Independent Timing per Drive

733 Flow Control

7331 PIO

73311 IORDY

73312 Pseudo DMA

7332 DMA

734 Interrupt Routing

735 Prefetching

736 LegacyNative Mapping Scheme

70 FUNCTIONAL DESCRIPTION

(Continued)

74 DMA Controller

741 DMA Engine

7411 Alignment

742 DMA Engine Protocol

7421 Scenario 1

74211 Bus Master Writes

74212 Bus Master Reads

7422 Scenario 2

74221 Bus Master Writes

74222 Bus Master Reads

7423 Scenario 3

74231 Bus Master Writes

74232 Bus Master Reads

7424 PCI Bus Request

74241 PCI Master Reads

74242 PCI Master Writes

743 Master Aborts

744 Target Aborts

745 Data Synchronization

7451 Normal

7452 Byte Count is Less than IDE transfer

size

7453 Byte Count is Greater than IDE transfer

size

7454 Transfer in Progress

746 Bus Master Programming Sequence

80 ELECTRICAL CHARACTERISTICS

81 Absolute Maximum Ratings

82 Recommended Operating Conditions

83 DC Electrical Characteristics

84 AC Timing Specifications

841 PCI Timing Specifications

842 ATAIDE Timing Specifications

843 Configuration Register Read Cycles

844 Configuration Register Write Cycles

845 Prefetch Cycles (Read Buffer Empty)

846 Prefetch Cycles (Read Buffer Not Empty)

847 Posted Write Cycles (Medium Decode)

848 Posted Write Cycles (Fast Decode)

849 IDE Non Data Read Cycles

8410 IDE Non Data Write Cycles

8411 DMA Cycles

90 APPLICATION INFORMATION

91 Power Control for IDE Drives

92 Native Mode Interrupt Support

93 DMA Bus Master Control Status Register

100 ERRATA

101 Target Mode

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