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ST8034HC 数据表(PDF) 20 Page - STMicroelectronics |
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ST8034HC 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 31 page ![]() Functional description ST8034HN, ST8034HC 20/31 DocID024511 Rev 2 The voltage supervisor monitors the VDDP, VDD, and VDD(INTF) voltages and provides both power-on reset (POR) and supply dropout detection during a card session. The supervisor threshold voltages for VDDP and VDD are set internally, and VDD(INTF) is set externally by an external resistor divider on the PORADJ pin, which provides additional voltage monitoring flexibility (this pin can be used for monitoring any external voltage, with adjustable threshold): Undervoltage (UVLO) threshold adjustment on the PORADJ input with the resistor divider: VDD(INTF) UVLO threshold (falling) = (R1+R2)/R2 x VTH(PORADJ) VDD(INTF) UVLO threshold (rising) = (R1+R2)/R2 x (VTH(PORADJ) + VHYST(PORADJ)) If the external resistor divider is not used, connect the PORADJ pin to VDD(INTF), then VDD(INTF) UVLO threshold = VTH(PORADJ). As long as VDDP, VDD or VDD(INTF) is less than the corresponding VTH + VHYS, the device remains inactive irrespective of the command line levels. After VDDP, VDD, and VDD(INTF) has reached a level higher than the corresponding VTH + VHYS, the device still remains inactive for the duration of tW, a defined reset pulse of approximately 8 ms (tW = 1024 x 1/fOSC(INT)LOW) when the output of the supervisor keeps the control logic in reset state. This is used to maintain the device in shutdown mode during the supply voltage power-on, see Figure 7. A deactivation sequence is performed when either VDD, VDDP or VDD(INTF) falls below the corresponding VTH. Figure 7. Voltage supervisor waveforms 6.3 Clock circuits The clock signal for the card (CLK output) is either provided by an external clock signal connected to the XTAL1 pin or generated by a crystal connected between the XTAL1 and XTAL2 pins. The ST8034 automatically detects if an external clock is connected to XTAL1, which eliminates the need for a separate clock source selection pin. Automatic clock source detection is performed on each activation command (falling edge of CMDVCC). The presence of an external clock on the XTAL1 pin is checked during a time window defined by the internal oscillator. If the external clock is detected, the crystal oscillator is stopped. If the clock is not detected, the crystal oscillator is started. When the external clock is used, the clock signal must be present on the XTAL1 pin before the CMDVCC falling edge. If the external clock is used, connect it to XTAL1 input and leave the XTAL2 pin floating. The XTAL1 pin can not be left floating, either a crystal or an external clock source needs to be connected, or the XTAL1 pin needs to be grounded. |
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