ST8034HC datasheet(22/31 Pages) STMICROELECTRONICS

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Functional description

ST8034HN, ST8034HC

22/31

DocID024511 Rev 2

The first side on which a falling edge occurs becomes the master. An anti-latch circuit

disables falling edge detection on the other side, making it the slave. After a time delay tD,

the logic 0 present on the master side is sent to the slave side. When the master side

returns logic 1, the slave side sends logic 1 during time delay (tW(PU)). After this sequence,

both master and slave sides return to their idle states.

The active pull-up feature (one-shot circuit) ensures fast low to high transitions, making the

ST8034 outputs capable of delivering more than 1 mA, up to an output voltage of 0.9 VCC, at

a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the

internal pull-up resistor value and load current. The current sent to and received from the

card's I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.

6.5

Shutdown mode

After a power-on reset, if CMDVCC is high, the ST8034 enters shutdown mode, ensuring

only the minimum number of circuits are active while the ST8034 waits for the

microcontroller to start a session.



All card contacts are inactive. The impedance between the contacts and GND is

approximately 200





I/OUC, AUX1UC, AUX2UC pins are in high impedance with the 10 k

 pull-up resistor

connected to VDD(INTF)



The voltage generators are stopped



The voltage supervisor is active



The internal oscillator runs at its lowest frequency (fOSC(INT)LOW).

ST8034HC 数据表(PDF) 22 Page - STMicroelectronics