DocID024511 Rev 2

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ST8034HN, ST8034HC

Functional description

Figure 8. External clock usage

ST8034HC, selected by the CLKDIV pin, see Table 12.

The frequency change is synchronous, meaning that after transition on the CLKDIV input,

the present clock period is completed and after that the new whole clock period starts,

therefore no clock period is shortened during the frequency switchover.

If an external crystal is used, the duty cycle on the CLK pin should be between 45% and

55%. If an external clock is connected to the XTAL1 pin, its duty cycle must be between 48%

and 52% so that the CLK output duty cycle is between 45% and 55%.

6.4

Input and output circuits

When the I/O and I/OUC pins are pulled high by a 9 k

10 k

Table 12. Clock frequency selection

ST8034HN

CLKDIV1 pin level

CLKDIV2 pin level

CLK frequency

Low

Low

Low

High

High

High

High

Low

ST8034HC

CLKDIV pin level

CLK frequency

High

Low