R5F100GC datasheet(77/202 Pages) RENESAS

77 / 202 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

C)

Page 77 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

2.4 AC Characteristics

(TA =

40 to +85C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

 VDD  5.5 V 0.03125

s

HS (high-

speed main)

mode

2.4 V

 VDD < 2.7 V 0.0625

s

LS (low-speed

main) mode

1.8 V

 VDD  5.5 V 0.125

s

Main

system

clock (fMAIN)

operation

LV (low-

voltage main)

mode

1.6 V

 VDD  5.5 V

0.25

s

Subsystem clock (fSUB)

operation

1.8 V

 VDD  5.5 V

28.5

30.5

31.3

s

2.7 V

 VDD  5.5 V 0.03125

s

HS (high-

speed main)

mode

2.4 V

 VDD < 2.7 V 0.0625

s

LS (low-speed

main) mode

1.8 V

 VDD  5.5 V 0.125

s

Instruction cycle (minimum

instruction execution time)

TCY

In the self

programming

mode

LV (low-

voltage main)

mode

1.8 V

 VDD  5.5 V

0.25

s

2.7 V

 VDD  5.5 V

1.0

20.0

MHz

2.4 V

 VDD < 2.7 V

1.0

16.0

MHz

1.8 V

 VDD < 2.4 V

1.0

8.0

MHz

fEX

1.6 V

 VDD < 1.8 V

1.0

4.0

MHz

External system clock

frequency

fEXS

kHz

2.7 V

 VDD  5.5 V

2.4 V

 VDD < 2.7 V

1.8 V

 VDD < 2.4 V

tEXH, tEXL

1.6 V

 VDD < 1.8 V

120

External system clock input

high-level width, low-level width

tEXHS, tEXLS

13.7

s

TI00 to TI07, TI10 to TI17 input

high-level width, low-level width

tTIH,

tTIL

1/fMCK+10

Note

4.0 V

 EVDD0  5.5 V

MHz

2.7 V

 EVDD0 < 4.0 V

MHz

1.8 V

 EVDD0 < 2.7 V

MHz

HS (high-speed

main) mode

1.6 V

 EVDD0 < 1.8 V

MHz

1.8 V

 EVDD0  5.5 V

MHz

LS (low-speed

main) mode

1.6 V

 EVDD0 < 1.8 V

MHz

TO00 to TO07, TO10 to TO17

output frequency

fTO

LV (low-voltage

main) mode

1.6 V

 EVDD0  5.5 V

MHz

4.0 V

 EVDD0  5.5 V

MHz

2.7 V

 EVDD0 < 4.0 V

MHz

1.8 V

 EVDD0 < 2.7 V

MHz

HS (high-speed

main) mode

1.6 V

 EVDD0 < 1.8 V

MHz

1.8 V

 EVDD0  5.5 V

MHz

LS (low-speed

main) mode

1.6 V

 EVDD0 < 1.8 V

MHz

1.8 V

 EVDD0  5.5 V

MHz

PCLBUZ0, PCLBUZ1 output

frequency

fPCL

LV (low-voltage

main) mode

1.6 V

 EVDD0 < 1.8 V

MHz

INTP0

1.6 V

 VDD  5.5 V

s

Interrupt input high-level width,

low-level width

tINTH,

tINTL

INTP1 to INTP11

1.6 V

 EVDD0  5.5 V

s

1.8 V

 EVDD0  5.5 V

250

Key interrupt input low-level

width

tKR

KR0 to KR7

1.6 V

 EVDD0 < 1.8 V

s

RESET low-level width

tRSL

s

(Note and Remark are listed on the next page.)

R5F100GC 数据表(PDF) 77 Page - Renesas Technology Corp

R5F100GC 数据表(HTML) 77 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

R5F100GC 数据表(PDF) 77 Page - Renesas Technology Corp

R5F100GC 数据表(HTML) 77 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载