R5F100GC datasheet(93/202 Pages) RENESAS

93 / 202 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

C)

Page 93 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 2.7 V

 EVDD0 < 4.0 V and 2.3 V  Vb  2.7 V

Maximum transfer rate =

{

Cb × Rb × ln (1 

2.0

Vb )} × 3

[bps]

Transfer rate

 2  {C

× Rb × ln (1



2.0

Vb )}

Baud rate error (theoretical value) =

× 100 [%]

(

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

This value as an example is calculated when the conditions described in the “Conditions” column are

met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.

Use it with EVDD0

 Vb.

The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 1.8 V

 EVDD0 < 3.3 V and 1.6 V  Vb  2.0 V

Maximum transfer rate =

[bps]

{

Cb × Rb × ln (1 

1.5

Vb )} × 3

Transfer rate

 2  {C

× Rb × ln (1



1.5

Vb )}

Baud rate error (theoretical value) =

× 100 [%]

(

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

This value as an example is calculated when the conditions described in the “Conditions” column are

met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When

20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by

using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,

see the DC characteristics with TTL input buffer selected.

UART mode connection diagram (during communication at different potential)

RL78 microcontroller

TxDq

RxDq

User device

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