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R5F104LED 数据表(PDF) 105 Page - Renesas Technology Corp |
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R5F104LED 数据表(HTML) 105 Page - Renesas Technology Corp |
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105 / 213 page  RL78/G14 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85 °C) R01DS0053EJ0330 Rev. 3.30 Page 105 of 208 Aug 12, 2016 (Notes, Caution, and Remarks are listed on the next page.) (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode LS (low-speed main) mode LV (low-voltage main) mode Unit MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 24 MHz < fMCK 14/fMCK —— ns 20 MHz < fMCK ≤ 24 MHz 12/fMCK —— ns 8 MHz < fMCK ≤ 20 MHz 10/fMCK —— ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK —ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 24 MHz < fMCK 20/fMCK —— ns 20 MHz < fMCK ≤ 24 MHz 16/fMCK —— ns 16 MHz < fMCK ≤ 20 MHz 14/fMCK —— ns 8 MHz < fMCK ≤ 16 MHz 12/fMCK —— ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK —ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 24 MHz < fMCK 48/fMCK —— ns 20 MHz < fMCK ≤ 24 MHz 36/fMCK —— ns 16 MHz < fMCK ≤ 20 MHz 32/fMCK —— ns 8 MHz < fMCK ≤ 16 MHz 26/fMCK —— ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK 16/fMCK —ns fMCK ≤ 4 MHz 10/fMCK 10/fMCK 10/fMCK ns SCKp high-/ low-level width tKH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 - 12 tKCY2/2 - 50 tKCY2/2 - 50 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 - 18 tKCY2/2 - 50 tKCY2/2 - 50 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - 50 ns SIp setup time (to SCKp ↑) Note 3 tSIK2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns SIp hold time (from SCKp ↑) Note 4 tKSI2 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns Delay time from SCKp ↓ to SOp output Note 5 tKSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 k Ω 2/fMCK + 120 2/fMCK + 573 2/fMCK + 573 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 k Ω 2/fMCK + 214 2/fMCK + 573 2/fMCK + 573 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rv = 5.5 k Ω 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns |
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