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R5F104LED 数据表(PDF) 109 Page - Renesas Technology Corp

部件名 R5F104LED
功能描述  True Low Power Platform
PDF  213 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104LED 数据表(HTML) 109 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85
°C)
R01DS0053EJ0330 Rev. 3.30
Page 109 of 208
Aug 12, 2016
Note 1.
The value must also be equal to or less than fMCK/4.
Note 2.
Use it with EVDD0
≥ Vb.
Note 3.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin products)/EVDD
tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance
(for the 30- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SCLr pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +85°C, 1.8 V
EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/2)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
LS (low-speed main)
mode
LV (low-voltage main)
mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Data setup time
(reception)
tSU:DAT
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 k
Ω
1/fMCK + 135 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 k
Ω
1/fMCK + 135 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 k
Ω
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 k
Ω
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
1.8 V
≤ EVDD0 < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
Ω
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
1/fMCK + 190 Note 3
ns
Data hold time
(transmission)
tHD:DAT
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 k
Ω
0
305
0
305
0
305
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 k
Ω
0
305
0
305
0
305
ns
4.0 V
≤ EVDD0 ≤ 5.5 V,
2.7 V
≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 k
Ω
0
355
0
355
0
355
ns
2.7 V
≤ EVDD0 < 4.0 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 k
Ω
0
355
0
355
0
355
ns
1.8 V
≤ EVDD0 < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
Ω
0
405
0
405
0
405
ns



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