TNETX3150A datasheet(44/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

RAMsize and number of nodes supported

The address capability for the various RAM sizes is given in Table 6 (repeated from RAMsize register definition).

Table 6. Address Capability for RAM Sizes

RAMsize

RAM SIZE

WORST

CASE

BEST

CASE

0x00

640

× 8

0x01

832

× 8

136

0x02

× 8

184

0x03

× 8

432

0x04

× 8

928

0x05

× 8

1920

0x06

16K

× 9

3904

0x07

32K

× 10

123

7880

0x08

64K

× 11

251

15816

0x09

128K

× 12

507

31688

0x0A

256K

× 13

1019

63432

0x0B

512K

× 14

2189

134 040

0x0C

× 15

4530

277 408

0x0D–0x0F

× 16

9211

564 144

The data in Table 6 shows a large range between the worst-case performance and the best-case performance.

For a 500-address system, 128K

× 12 is needed. A 1000 address system requires 256K × 13. A 2000 address

system requires 512K

× 14, where K = 1024 for binary-sized memories.

The difference between the best and worst case at each row depends on the similarity (when viewed in 5-bit

groups) of the addresses entered into the table. If addresses are sequential, there is maximal table sharing, and

the most addresses fit into the smallest space. If addresses are widely spaced with respect to the 5-bit groups,

there is minimal table sharing, because each 32-entry table has only one entry at each level. This requires the

most SRAM per address.

Although the TNETX15AE is designed to work in a CPU-less environment, access to the internal registers is

useful for the following reasons:

D Setting/changing port assignments

D Setting operational modes (startup options)

D Resetting the device (software reset)

D Management-based access and control of the lookup table

D Statistics gathering

D Diagnostic operations

D Communicating with attached PHYs through the MII

D Reading/writing to an external EEPROM

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