TNETX3150A datasheet(17/78 Pages) TI

17 / 78 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

internal register descriptions

revision register, revision at 0x00 (DIO)

BIT

(MOST-SIGNIFICANT BIT)

(LEAST-SIGNIFICANT BIT)

Product code

Revision

Initial values after reset

This register contains the revision code for the device. The initial revision code is hardwired to 0x10. This register

is read only, and writes to it are ignored.

SRAM size-select register, RAMsize at 0x01 (DIO)

The RAMsize register can be written to only when the START bit in the control register is set to 0. This register

is automatically loaded from the EEPROM when the RESET terminal is asserted low, or when LOAD in the

control register is set.

BIT

Reserved

RSIZE

Initial values after reset

BIT

NAME

FUNCTION

7–4

Reserved

Writes to this location are ignored and are read as 0.

3–0

RSIZE

Ram size select. This field indicates the size of the external SRAM, and has a bearing on the number of addresses that

the TNETX15AE supports. The TNETX15AE uses this field to determine how many tables to initialize as part of the reset

sequence by indicating how many address lines to use. The TNETX15AE uses external SRAM for tables of pointers

used in address decoding and for table end pointers (the two-word address descriptors). This field can be written only

when the START bit is 0 and reset is not active. This field also is loaded from the EEPROM interface during auto load.

Code values are as follows:

RAMsize

RAM

WORST

SIZE

CASE

0x00

640

× 82

0x01

832

× 82

0x02

× 83

0x03

× 87

0x04

× 814

0x05

× 828

0x06

16K

× 959

0x07

32K

× 10

123

0x08

64K

× 11

251

0x09

128K

× 12

507

0x0A

256K

× 13

1019

0x0B

512K

× 14

2189

0x0C

× 15

4530

0x0D to 0x0F

× 16

9211

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