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PRELIMINARY TECHNICAL DATA

AD9953

The modes of operation are summarized in the table below. Please note the PLL multiplier is

controlled via the CFR2<7:3> bits, independently of the CFR2<0> bit.

ClkModeSelect

CFR1<4>

CFR2<7:3>

SYSTEM

CLOCK

Frequency

Range (MHz)

HIGH

LOW

3 < M < 21

Fclk = Fosc x M

80 < Fclk < 400

HIGH

LOW

M < 4 or M > 20

Fclk = Fosc

20 < Fclk < 30

HIGH

Fclk = 0

LOW

3 < M < 21

Fclk = Fref x M

80 < Fclk < 400

LOW

M < 4 or M > 20

Fclk = Fref

5 < Fclk < 400

Table 2 Clock Input Modes of Operation

Phase Locked Loop (PLL)

The PLL allows multiplication of the REFCLK frequency. Control of the PLL is accomplished by

programming the 5-bit REFCLK Multiplier portion of Control Function Register #2, bits <7:3>.

When programmed for values ranging from 04h – 14h (4-20 decimal), the PLL multiplies the

REFCLK input frequency by the corresponding decimal value. The maximum output frequency of

the PLL is restricted to 400MHz, however. Whenever the PLL value is changed, the user should

be aware that time must be allocated to allow the PLL to lock (approximately 1ms).

The PLL is bypassed by programming a value outside the range of 4-20 (decimal). When

bypassed, the PLL is shut down to conserve power.

DAC Output

The AD9953 incorporates an integrated 14-bit current output DAC. Two complementary outputs

provide a combined full-scale output current (Iout). Differential outputs reduce the amount of

common-mode noise that might be present at the DAC output, offering the advantage of an

increased signal-to-noise ratio. The full-scale current is controlled by means of an external resistor

(Rset) connected between the DAC_Rset pin and the DAC ground (AGND). The full-scale current

is proportional to the resistor value as follows:

Rset = 39.19/Iout

The maximum full-scale output current of the combined DAC outputs is 15mA, but limiting the

output to 10mA provides the best spurious-free-dynamic-range (SFDR) performance. The DAC

output compliance range is AVDD+0.250V to AVDD-375V. Voltages developed beyond this

range will cause excessive DAC distortion and could potentially damage the DAC output circuitry.

Proper attention should be paid to the load termination to keep the output voltage within this

compliance range.

Serial IO Port

REV. PrB 1/30/03

Page 12

Analog Devices, Inc.

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