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AD9953ASV 数据表(PDF) 35 Page - Analog Devices |
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AD9953ASV 数据表(HTML) 35 Page - Analog Devices |
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35 / 42 page ![]() PRELIMINARY TECHNICAL DATA AD9953 0 1 0 SyncClk Disable D Q D Q D Q OSK Profile<1:0> I/O UPDATE Edge Detection Logic SYNCCLK Gating Register Memory I/O Buffer Latches SCLK SDI CS TO CORE LOGIC SYSCLK ÷4 Figure D- I/O Synchronization Block Diagram Data[1] Data[1] Data(2) Data(2) Data(3) Data(3) AB SYSCLK SYNCLK I/O Update Data in Registers Data in I/O Buffers The device registers an I/O Update at point A. The data is tranferred from the asynchronously loaded I/O buffers at point B. Figure E - I/O Synchronization Timing Diagram REV. PrB 1/30/03 Page 35 Analog Devices, Inc. |
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