AD6650BBC1 datasheet(15/28 Pages) AD

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Preliminary Technical Data

AD6650

REV. PrJ 02/27/2003

ARCHITECTURE

The AD6650 is a mixed-signal received signal processor

intended for direct IF sampling radios requiring high symbol

rate. It has been optimized for the demanding filtering

requirements of GSM and EDGE.

The AD6650 has five signal processing stages: a digital

VGA, I&Q Demodulators, 7th Order Low Pass Filters, dual

wideband ADC, and Digital Filtering and Control Stage.

Programming and control is accomplished via serial and

microprocessor interfaces.

DVGA

A gain ranging digital VGA is used to extend the dynamic

range of the input signal and prevent signal clipping at the

ADC input.

I&Q Demodulators

Frequency translation is accomplished with I&Q demodulators.

Real data entering this stage is separated into in-phase (I) and

quadrature (Q) components. This stage translates the input

signal from an intermediate frequency (IF) to a baseband

frequency.

Low Pass Filters

Following frequency translation is a 7th Order Low Pass

Active Filter with a 3.5 MHz Bandwidth and RC calibration.

Dual ADCs

The ADC is implemented by providing dual track and holds

in front of an AD9238 ADC core. In front of each ADC is a

MUX operating at 52 MSPS.

VCO/PLL

A voltage controlled oscillator and phase locked loop

circuit generates the appropriate IF frequency for the

demodulators.

DIGITAL FILTERS

Following the analog frequency translation is a fourth order

Cascaded Integrator Comb (CIC4) filter whose response is

defined by the decimation rate.

IIR Stage Next

The final stage is a sum-of-products FIR filter with

programmable 20-bit coefficients, and decimation rates

programmable from 1 to 4. The RAM Coefficient FIR filter

(RCF in the Functional Block Diagram) can handle a maximum

of 48 taps.

The overall filter response for the AD6650 is the composite of

all decimating. Each successive filter stage is capable of

narrower transition bandwidths but requires a greater number of

CLK cycles to calculate the output. More decimation in the first

filter stage will minimize overall power consumption. Data from

the chip is interfaced to the DSP via a high-speed synchronous

serial port.

Theory of Operation

AGC LOOP

The AGC consists of three gain control loops; a slow loop

following the ADC, a Fast Attack (FA) loop following the base

band filter, and the Fast Decay (FD) loop following the

decimation filters.

Slow Loop

The slow loop is the main loop and has a ‘Loop gain’ parameter

(p41) associated with it. This parameter controls the rate of

change of the gain and should always be less than 1. The default

loop gain used is 1/256. The slow loop attempts to maintain the

signal entering the ADC at a given level, which is referred to as

the ‘Requested level’ (p5). This level is specified to the loop in

dBFS. This level can be between 0dBFS and –24dBFS of the

converter in .094dB resolution. The default value is –6.02

dBFS. The slow loop has a ‘peak detect’ function, the period of

which can be set by the user (p1). This ‘peak detect’ period can

be set to 1/4 of a symbol period or greater to prevent the AGC

loop from gaining off the envelope of the EDGE signal. This

works since the Peak Detector works off of the function

dB(max(|I|,|Q|)) which reflects all of the IQ samples back into

one quadrant of the IQ plane. At a 26MHz sampling frequency,

1 symbol period turns out to be 96 clock cycles; therefore, to

obtain a peak detect period of 1/4 symbol, the period should be

set to 24 samples.

Fast Attack Loop

The FA loop is based off of an analog threshold detector that

prevents overdrive of the analog signal path. In a situation that

could potentially overdrive the converter, the FA loop takes over

from the slow loop and decreases the gain to the VGA front end.

The step size used for the FA loop is programmable between 0

and 1.504dB in .094 dB steps(p0). The FA loop also has a

counter, which is programmable between 1 and 16. When

initialized to ‘Count+1’, the FA loop decreases the gain for

‘Count+1’ clock cycles when the threshold is crossed.

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