AD6650BBC1 datasheet(22/28 Pages) AD

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Preliminary Technical Data

AD6650

REV. PrJ 02/27/2003

External Memory Map

A[2:0]

Name

Comment

111

Access Control Register

(ACR)

7: Auto Increment

6: Broadcast

5-2: Instruction[3:0]

1-0: A[9:8]

110

Channel Address Register

(CAR)

7-0: A[7:0]

101

Special Function Register 2

(SF2)

AGC sync Enable

DC correction sync enable

PN sync enable

3-1: Reserved

Issue soft sync

100

Special Function Register 1

(SF1)

First Sync only

Enable edge-sensitivity

3-1: Reserved

011

Special Function Register 0

(SF0)

7-4: Reserved

Status of Channel B

Enable Channel B

Status of Channel A

Enable Channel A

010

Data Register 2 (DR2)

7-4: Reserved

3-0: D[19:16]

001

Data Register 1 (DR1)

15-8: D[15:8]

000

Data Register 0 (DR0)

7-0: D[7:0]

Table xx. External Memory Map

Access Control Register (ACR)

The Access Control Register serves to define the channel or

channels that receive an access from the micro-port or I2C

port.

Bit 7 of this register is the Auto-Increment bit. If this bit is a

1 then the CAR register described below will increment its

value after every access to the channel. This allows blocks

of address space such as Coefficient Memory to be

initialized more efficiently.

Bit 6 of the register is the Broadcast bit and determines how bits

5-2 are interpreted. The Broadcast bit should be set high so that

bits 5-2, which are referred to as Instruction bits (Instruction

[3:0]), allows a single or multiple (up to 4) AD6650 chip(s) to be

configured simultaneously There are 10 possible instructions

that are defined in the table below. The x’s in the table represent

don’t cares in the digital decoding.

Microport Instructions

Instruction

Comment:

0000

All Chips will get the access.

0001

All Chips will get the access.

0010

All Chips will get the access.

0100

All Chips will get the access.

1000

All Chips with Chip_ID[0] =xxx 0 will get the

access.1

1001

All Chips with Chip_ID[0] = xxx1 will get the

access.1

1100

All Chips with Chip_ID[1:0] = xx00 will get the

access.1

1101

All Chips with Chip_ID[1:0] = xx01 will get the

access.1

1110

All Chips with Chip_ID[1:0] = xx10 will get the

access.1

1111

All Chips with Chip_ID[1:0] = xx11 will get the

access.1

1A[9:8] bits control which channel is decoded for the access.

Table xx. Microport Instructions

When broadcast is enabled (bit 6 set high) read back is not

valid because of the potential for internal bus contention.

Therefore, if read back is subsequently desired, the

broadcast bit should be set low.

Bits 1-0 of this register are address bits that decode which of

the two channels are being accessed. Because the channels

of the AD6650 cannot be programmed independently, these

bits should be set to 0.

Channel Address Register (CAR)

This register represents the 8-bit internal address of each

channel. If the Auto-Increment bit of the ACR is 1 then this

value will be incremented after every access to the DR0

this address. The Channel Address register cannot be read

back while the Broadcast bit is set high.

Special Function Registers

The AD6650 has three special function registers, SF0, SF1,

and SF2 that control synchronizing and enabling the

channels. SF0 is the channel enable register, SF1 is the pin-

sync register, and SF2 is the soft-sync register. For SF0, bits

0 and 2 allow the channels A and B, respectively to come

out of sleep based on the method selected in SF1.Bits 1 and

3 are read-only and indicate whether or not channels A and

B, respectively are active. A 1 indicates the channel is active

and a 0 indicates it is not active. Bits 4 through 7 are

unused.

For SF1, if bit 0 is set to 1,then both channels will wait for a

pulse to appear on the SYNC pin before coming out of sleep;

otherwise, the channels will assume a soft start is desired

and wait for the start hold-off counter to issue a sync. When

bit 5 is set, both channels ignore all subsequent attempts to

resync once they are awake.

For SF2, bit 0 tells the startup block to run the start hold-off

counter from the value programmed into the start hold-off

counter control register and issue a sync when done. Bits 4-

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