AD6650BBC1 datasheet(16/28 Pages) AD

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Preliminary Technical Data

AD6650

REV. PrJ 02/27/2003

Fast Decay Loop

The Fast Decay (FD) loop is a fast loop that increases the gain

when the signal falls below a threshold during a deep channel

fade or on the Ramp Down. The fast loop accomplishes this

task by looking at two outputs. The first is the peak signal plus

blocker level at the ADC output (which includes the signal and

any blockers that may be passed through by the SAW filter).

The second is the peak signal level after the decimation filters

and a Blocker Reject Filter have attenuated the blockers. There

are two programmable levels that determine when this loop is

activated: the Signal Plus Blocker level (SPB_level) and the

Signal level (SIG_level). Both these levels are defined in dBFS.

Default values stand at –40dBFS for the SPB_level and –

60dBFS for the SIG_level. When the ‘wideband’ signal is below

the SPB level (p12) and ‘narrowband’ information is below the

Signal level (p13), the FD loop is activated. This loop overrides

the slow loop and has a programmable step size (p7) (currently

set at 0.094dB) and a programmable peak detect period (p6)

currently set at 4 samples at 1.08MHz.

FOURTH ORDER CASCADED

INTEGRATOR COMB FILTER

The CIC4 processing stage implements a sharp fixed-

coefficient decimating filter, which is driven by the 12 bit

Analog to Digital converter. The maximum input rate into

this filter is ADCOUTPUT, which cannot exceed 26 MHz.

The decimation ratio, MCIC4, may be programmed from 8

to 32 (all integer values). The frequency response of the

filter is given by Equation x. The gain and passband droop

of CIC4 should be calculated by these equations. Both

parameters may be compensated for in the IIR stage.

)

(













−

⋅

−

CIC

sin

)

(

























⋅













⋅

ADC

CIC

The scale factor, SCIC4 is a programmable unsigned integer

between 12 and 20. It serves to control the attenuation of the data

into the CIC4 stage in 6 dB increments. For the best dynamic

range, SCIC4 should be set to the smallest value possible (lowest

attenuation) without creating an overflow condition.

()

() 12

log

−

ceil

CIC

The output rate of this stage is given by equation x.

CIC

OUTPUT

SAMP

ADC

≤

CIC4 Rejection

Table xx illustrates the amount of bandwidth in percentage of the

clock rate that can be protected with various decimation rates

and alias rejection specifications. The maximum input rate into

the CIC4 is 26 MHz, as mentioned above. As in Table xx, these

are the ½ bandwidth characteristics of the CIC4.

Table x. SSB CIC4 Alias Rejection Table

-50

-60

-70

-80

-90

-100

2.602 2.751 2.867 2.957 3.027 3.080

2.311 2.444 2.547 2.627 2.690 2.737

10 2.078 2.199 2.291 2.364 2.420 2.463

11 1.889 1.998 2.083 2.148 2.200 2.239

12 1.731 1.831 1.909 1.969 2.016 2.052

13 1.597 1.690 1.761 1.817 1.861 1.894

14 1.483 1.569 1.635 1.687 1.728 1.759

15 1.384 1.464 1.526 1.575 1.613 1.641

16 1.297 1.373 1.431 1.476 1.512 1.539

17 1.221 1.292 1.346 1.389 1.423 1.448

18 1.153 1.220 1.272 1.312 1.344 1.368

19 1.092 1.156 1.205 1.243 1.273 1.296

20 1.037 1.098 1.144 1.181 1.209 1.231

21 0.988 1.045 1.090 1.124 1.152 1.172

22 0.943 0.998 1.040 1.073 1.099 1.119

23 0.902 0.954 0.995 1.027 1.051 1.070

24 2.602 2.751 2.867 2.957 3.027 3.080

25 0.830 0.878 0.915 0.944 0.967 0.985

26 0.798 0.844 0.880 0.908 0.930 0.947

27 0.768 0.813 0.847 0.874 0.896 0.912

28 0.741 0.784 0.817 0.843 0.864 0.879

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