AD6650BBC1 datasheet(25/28 Pages) AD

25 / 28 page

Preliminary Technical Data

AD6650

REV. PrJ 02/27/2003

AD6650 Memory Map

CH Address

Bit Width

Bit Definitions

0 (Hex)

Clock Divider Control

0: Clock_DIV

1: Divide by 2

0: No Divide

PLL Register 0

PLL Register 1

PLL Register 2

PLL Register 3

Clamp Control

1: Disable B

0: Disable A

Aux DAC A

Aux_DACA

Aux DAC B

Aux_DACB

Aux DAC Control

7-5: FS Current Adjust B

4: Enable DAC B

3-1: FS Current Adjust A

0: Enable DAC A

ADC Dither Control

1: High Dither Power

0: Enable Dither

DC Correction BW

15-0: Correction BW

DC Correction Control

Multiply by .75

5-2: Scalar

1: PN_EN

0: Enable

AGC Control 0

3: Force VGA Gain

2: FD_Enable

1: FA_Enable

0: Slow Loop Enable

AGC Control 1

8-0: VGA_Gain

AGC Control 2

15-8 Hysterisis

7-0: Requested Level

AGC Control 3

10-8: Loop Gain-Exp

7-0: Loop Gain-Mant

AGC Control 4

12-10: FD_Step-1

9-8: FA_Thresh

7-4: FA_count

3-0: FA_Step-1

AGC Control 5

15-8: SpB Peak Detect Period

7-0: S Peak Detect Period

AGC Control 6

11-0: FD_S Threshold

AGC Control 7

11-0: FD_SpB Threshold

Start Hold-Off Counter

CIC4 Decimation

MCIC4-1

CIC4 Scale

CIC4_scale

IIR Control Register

SYNC_MASK

RCF Decimation

MRCF-1

RCF Decimation Phase

PRCF

RCF Coefficient Offset

CORCF

RCF Taps

NTaps-1

RCF Scale Register

1-0: Scale

BIST for A-I

BIST-I/DATA_I

BIST for A-Q

BIST-Q/DATA_Q

BIST for B-I

BIST-I/DATA_I

AD6650BBC1 数据表(PDF) 25 Page - Analog Devices

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