ADAU1361BCPZ-R7 datasheet(32/81 Pages) AD

32 / 81 page

ADAU1361

Rev. C | Page 31 of 80

Digital Microphone Input

ANALOG-TO-DIGITAL CONVERTERS

When using a digital microphone connected to the JACKDET/

MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008)

must be set to 10 to enable the microphone input and disable

the jack detection function. The ADAU1361 must operate in

master mode and source BCLK to the input clock of the digital

microphone.

The ADAU1361 uses two 24-bit Σ-Δ analog-to-digital con-

verters (ADCs) with selectable oversampling ratios of 64× or

128× (selected by Bit 3 in Register R17, Address 0x4017).

ADC Full-Scale Level

The full-scale input to the ADCs (0 dBFS) depends on AVDD.

At AVDD = 3.3 V, the full-scale input level is 1.0 V rms. This

full-scale analog input will output a digital signal at −1.38 dBFS.

This gain offset is built into the ADAU1361 to prevent clipping.

The full-scale input level scales linearly with the level of AVDD.

The digital microphone signal bypasses record path mixers and

ADCs and is routed directly into the decimation filters. The

digital microphone and ADCs share decimation filters and,

therefore, both cannot be used simultaneously. The digital

microphone input select bit, INSEL, can be set in Register R19

(ADC control register, Address 0x4019). Figure 35 depicts the

digital microphone interface and signal routing.

For single-ended and pseudo-differential signals, the full-scale

value corresponds to the signal level at the pins, 0 dBFS.

The full differential full-scale input level is measured after the

differential amplifier, which corresponds to −6 dBFS at each pin.

JDFUNC[1:0]

DIGITAL MICROPHONE

INTERFACE

LEFT

CHANNEL

RIGHT

CHANNEL

TO JACK

DETECTION

CIRCUIT

JACKDET/MICIN

RIGHT

ADC

LEFT

ADC

DECIMATORS

R19: ADC CONTROL

INSEL

R2: DIGITAL MICROPHONE/

JACK DETECTION

CONTROL

Signal levels above the full-scale value cause the ADCs to clip.

Digital ADC Volume Control

The digital ADC volume can be attenuated using Register R20 (left

input digital volume register, Address 0x401A) and Register R21

(right input digital volume register, Address 0x401B).

High-Pass Filter

By default, a high-pass filter is used in the ADC path to remove

dc offsets; this filter can be enabled or disabled in Register R19

(ADC control register, Address 0x4019). At fS = 48 kHz, the

corner frequency of this high-pass filter is 2 Hz.

Figure 35. Digital Microphone Interface Block Diagram

Microphone Bias

The MICBIAS pin provides a voltage reference for electret analog

microphones. The MICBIAS voltage is set in Register R10

(record microphone bias control register, Address 0x4010). In

this register, the MICBIAS output can be enabled or disabled.

Additional options include high performance operation and a

gain boost. The gain boost provides two different voltage biases:

0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-

mance bit increases supply current to the microphone bias

circuit to decrease rms input noise.

The MICBIAS pin can also be used to cleanly supply voltage

to digital microphones or analog microphones with separate

power supply pins.

ADAU1361BCPZ-R7 数据表(PDF) 32 Page - Analog Devices

ADAU1361BCPZ-R7 数据表(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载