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ADAU1361BCPZ-R7 数据表(PDF) 13 Page - Analog Devices

部件名 ADAU1361BCPZ-R7
功能描述  Audio Codec with Integrated PLL
PDF  81 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1361BCPZ-R7 数据表(HTML) 13 Page - Analog Devices

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ADAU1361
Rev. C | Page 12 of 80
DIGITAL TIMING DIAGRAMS
BCLK
LRCLK
DAC_SDATA
LEFT-JUSTIFIED
MODE
LSB
DAC_SDATA
I2S MODE
DAC_SDATA
RIGHT-JUSTIFIED
MODE
tBIH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tLIS
tSIS
tSIH
tSIH
tSIS
tSIS
tSIH
tSIS
tSIH
tLIH
tBIL
Figure 2. Serial Input Port Timing
BCLK
LRCLK
ADC_SDATA
LEFT-JUSTIFIED
MODE
LSB
ADC_SDATA
I2S MODE
ADC_SDATA
RIGHT-JUSTIFIED
MODE
tBIH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tSODM
tBIL
tSODM
tSODM
Figure 3. Serial Output Port Timing



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