ADAU1361BCPZ-R7 datasheet(39/81 Pages) AD

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ADAU1361

Rev. C | Page 38 of 80

CONTROL PORTS

The ADAU1361 can operate in one of two control modes:

•

I2C control

•

SPI control

The ADAU1361 has both a 4-wire SPI control port and a

2-wire I2C bus control port. Both ports can be used to set the

registers. The part defaults to I2C mode, but it can be put into

SPI control mode by pulling the CLATCH pin low three times.

The control port is capable of full read/write operation for all

addressable registers. The ADAU1361 must have a valid master

clock in order to write to all registers except for Register R0

(Address 0x4000) and Register R1 (Address 0x4002).

All addresses can be accessed in both a single-address mode

or a burst mode. The first byte (Byte 0) of a control port write

contains the 7-bit chip address plus the R/W bit. The next two

bytes (Byte 1 and Byte 2) together form the subaddress of the

be two bytes long because the memory locations within the

ADAU1361 are directly addressable and their sizes exceed the

range of single-byte addressing. All subsequent bytes (starting

with Byte 3) contain the data. The number of bytes per word

depends on the type of data that is being written.

The control port pins are multifunctional, depending on the

mode in which the part is operating. Table 20 describes these

multiple functions.

Table 20. Control Port Pin Functions

Pin Name

I2C Mode

SPI Mode

SCL/CCLK

SCL: input clock

CCLK: input clock

SDA/COUT

SDA: open-collector

input/output

COUT: output

ADDR1/CDATA

I2C Address Bit 1: input

CDATA: input

ADDR0/CLATCH

I2C Address Bit 0: input

CLATCH: input

BURST MODE WRITING AND READING

Burst mode addressing, where the subaddresses are automatically

incremented at word boundaries, can be used for writing large

amounts of data to contiguous registers. This increment happens

automatically after a single-word write or read unless a stop condi-

tion is encountered (I2C) or CLATCH is brought high (SPI). A

burst write starts like a single-word write, but following the first

data-word, the data-word for the next immediate address can be

written immediately without sending its two-byte address.

The registers in the ADAU1361 are one byte wide with the

exception of the PLL control register, which is six bytes wide.

The autoincrement feature knows the word length at each

subaddress, so the subaddress does not need to be specified

manually for each address in a burst write.

The subaddresses are autoincremented by 1 following each

read or write of a data-word, regardless of whether there is a

valid register word at that address. Address holes in the register

map can be written to or read from without consequence. In

the ADAU1361, these address holes exist at Address 0x4001,

Address 0x4003 to Address 0x4007, Address 0x402E, and

Address 0x4032 to Address 0x4035. A single-byte write to these

registers is ignored by the ADAU1361, and a read returns a

single byte 0x00.

I2C PORT

The ADAU1361 supports a 2-wire serial (I2C-compatible)

microprocessor bus driving multiple peripherals. Two pins,

serial data (SDA) and serial clock (SCL), carry information

between the ADAU1361 and the system I2C master controller.

In I2C mode, the ADAU1361 is always a slave on the bus,

meaning that it cannot initiate a data transfer. Each slave device

is recognized by a unique address. The address and R/W byte

format is shown in

. The address resides in the first

seven bits of the I2C write. Bits[5:6] of the I2C address for the

ADAU1361 are set by the levels on the ADDR1 and ADDR0

pins. The LSB of the address—the R/

Table 21

W bit—specifies either a

read or write operation. Logic Level 1 corresponds to a read

operation, and Logic Level 0 corresponds to a write operation.

Table 21. ADAU1361 I2C Address and Read/Write Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

ADDR1

ADDR0

R/W

The SDA and SCL pins should each have a 2 kΩ pull-up resistor

on the line connected to it. The voltage on these signal lines

should not be higher than IOVDD (1.8 V to 3.3 V).

Addressing

Initially, each device on the I2C bus is in an idle state and

monitors the SDA and SCL lines for a start condition and

the proper address. The I2C master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDA while SCL remains high. This indicates that an address/

data stream follows. All devices on the bus respond to the start

condition and shift the next eight bits (the 7-bit address plus the

R/W bit) MSB first. The device that recognizes the transmitted

address responds by pulling the data line low during the ninth

clock pulse. This ninth bit is known as an acknowledge bit. All

other devices withdraw from the bus at this point and return to

the idle condition.

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