ADAU1361BCPZ-R7 datasheet(1/81 Pages) AD

部件名	ADAU1361BCPZ-R7

功能描述	Audio Codec with Integrated PLL

PDF	81 Pages

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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Stereo, Low Power, 96 kHz, 24-Bit

Audio Codec with Integrated PLL

ADAU1361

Rev. C

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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

24-bit stereo audio ADC and DAC: >98 dB SNR

Sampling rates from 8 kHz to 96 kHz

Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V

6 analog input pins, configurable for single-ended or

differential inputs

Flexible analog input/output mixers

Stereo digital microphone input

Analog outputs: 2 differential stereo, 2 single-ended stereo,

1 mono headphone output driver

PLL supporting input clocks from 8 MHz to 27 MHz

Analog automatic level control (ALC)

Microphone bias reference voltage

Analog and digital I/O: 1.8 V to 3.65 V

I2C and SPI control interfaces

Digital audio serial data I/O: stereo and time-division

multiplexing (TDM) modes

Software-controllable clickless mute

Software power-down

32-lead, 5 mm × 5 mm LFCSP

−40°C to +85°C operating temperature range

APPLICATIONS

Smartphones/multimedia phones

Digital still cameras/digital video cameras

Portable media players/portable audio players

Phone accessories products

GENERAL DESCRIPTION

The ADAU1361 is a low power, stereo audio codec that supports

stereo 48 kHz record and playback at 14 mW from a 1.8 V analog

supply. The stereo audio ADCs and DACs support sample rates

from 8 kHz to 96 kHz as well as a digital volume control. The

ADAU1361 is ideal for battery-powered audio and telephony

applications.

The record path includes an integrated microphone bias circuit

and six inputs. The inputs can be mixed and muxed before the

ADC, or they can be configured to bypass the ADC. The

ADAU1361 includes a stereo digital microphone input.

The ADAU1361 includes five high power output drivers (two

differential and three single-ended), supporting stereo head-

phones, an earpiece, or other output transducer. AC-coupled

or capless configurations are supported. Individual fine level

controls are supported on all analog outputs. The output mixer

stage allows for flexible routing of audio.

The serial control bus supports the I2C and SPI protocols. The

serial audio bus is programmable for I2S, left-/right-justified,

and TDM modes. A programmable PLL supports flexible clock

generation for all standard integer rates and fractional master

clocks from 8 MHz to 27 MHz.

FUNCTIONAL BLOCK DIAGRAM

HP JACK

DETECTION

REGULATOR

INPUT

MIXERS

ALC

MICROPHONE

BIAS

PLL

LINN

LINP

LAUX

JACKDET/MICIN

RINP

RINN

RAUX

MICBIAS

LHP

LOUTN

LOUTP

ADAU1361

RHP

MONOOUT

ROUTP

ROUTN

OUTPUT

MIXERS

DAC

DIGITAL

FILTERS

ADC

DIGITAL

FILTERS

DAC

ADC

SDA/

COUT

I2C/SPI

CONTROL PORT

SERIAL DATA

INPUT/OUTPUT PORTS

MCLK ADC_SDATA

SCL/

CCLK

ADDR1/

CDATA

ADDR0/

CLATCH

DAC_SDATA

Figure 1.

类似零件编号 - ADAU1361BCPZ-R7

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Analog Devices	ADAU1361BCPZ-R7	1Mb / 80P	Audio Codec 8/2018-Rev. C to Rev. D
Analog Devices	ADAU1361BCPZ-R7	1Mb / 78P	Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL Rev. E

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