ST92F120 datasheet(52/324 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

(231FFDh). The second write access, with Pro-

gram Data matching with NVPWD[1:0] content, re-

sets the PWOK bit of NVWPR.

These two registers can be accessed only in write

mode (a read access returns FFh).

3.6.2 Temporary Unprotection

On user request the memory can be configured so

as to allow the temporary unprotection also of all

access protections bits of NVAPR (write protection

bits of NVWPR are always temporarily unprotecta-

ble).

Bit APEX can be temporarily disabled by execut-

ing the Set Protection operation and writing 1 into

this bit, but only if this write instruction is executed

from an internal memory (Flash and Test Flash ex-

cluded).

Bit APEE can be temporarily disabled by execut-

ing the Set Protection operation and writing 1 into

this bit, but only if this write instruction is executed

from the memory itself to unprotect (EEPROM).

Bits APRO and APBR can be temporarily disabled

through a direct write at NVAPR location, by over-

writing at 1 these bits, but only if this write instruc-

tion is executed from the memory itself to unpro-

tect.

To restore the access protection bits it needs to re-

set the micro or to execute a Set Protection opera-

tion and write 0 into the desired bits.

When an internal memory (Flash, TestFlash or

EEPROM) is protected in access, also the data ac-

cess through a DMA of a peripheral is forbidden (it

returns FFh). To read data in DMA mode from a

protected memory, first it is necessary to tempo-

rarily unprotect that memory.

The temporary unprotection allows also to update

a protected code.

3.7 FLASH IN-SYSTEM PROGRAMMING

The Flash memory can be programmed in-system

through a serial interface (SCI0).

Exiting from reset, the ST9 executes the initializa-

tion from the TestFlash code (written in Test-

Flash), where it checks the value of the SOUT0

pin. If it is at 0, this means that the user wishes to

update the Flash code, otherwise normal execu-

tion continues. In this second case, the TestFlash

code reads the reset vector.

If the Flash is virgin (read content is always FFh),

its reset vector contains FFFFh. This is interpreted

by the TestFlash code as a flag indicating that the

Flash memory is virgin and needs to be pro-

grammed. If the value 1 is detected on the SOUT0

pin and the Flash is virgin, a HALT instruction is

executed, waiting for a hardware Reset.

3.7.1 Code Update Routine

The TestFlash Code Update routine is called auto-

matically if the SOUT0 pin is held low during pow-

er-on.

The Code Update routine performs the following

operations:

Enables the SCI0 peripheral in synchronous

mode

Transmits a synchronization datum (25h);

Waits for an address match (23h) with a timeout

of 10ms (@ fOSC 4 MHz)

If the match is not received before the timeout,

the execution returns to the Power-On routine

If the match is received, the SCI0 transmits a

new datum (21h) to tell the external device that

it is ready to receive the data to be loaded in

RAM (that represents the code of the in-system

programming routine).

Receives two data representing the number of

bytes to be loaded (max. 4 Kbytes)

Receive the specified number of bytes (each

one preceded by the transmission of a Ready to

Receive character: (21h) and writes them in

internal RAM starting from address 200010h.

The first 4 words should be the interrupt vectors

of the 4 possible SCI interrupts, to be used by

the in-system programming routine.

Transmit a last datum (21h) as a request for end

of communications.

Receives

the

end

communication

confirmation datum (any byte other than 25h).

Resets all the unused RAM locations to FFh;

Calls address 200018h in internal RAM.

After completion of the in-system programming

routine, an HALT instruction is executed and an

Hardware Reset is needed.

The Code Update routine initializes the SCI0 pe-

ripheral as shown in the following table:

Table 12. SCI0 Registers (page 24) initialization

Value

Notes

IVR - R244

10h

Vector Table in 0010h

ACR - R245

23h

Address Match is 23h

IDPR - R249

00h

SCI interrupt priority is 0

CHCR - R250

83h

8 Data Bits

CCR - R251

E8h

rec. clock: ext RXCLK0

trx clock: int CLKOUT0

BRGHR - R252

00h

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