Data Sheet

AD6657A

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 13 are not currently supported for this device.

Table 13. Memory Map Registers

Addr.

(Hex)

Register

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

(Hex)

Comments

Chip Configuration Registers

0x00

SPI port

configuration

(global)

Open

LSB first

Soft reset

1

1

Soft reset

LSB first

Open

0x18

Nibbles are

mirrored so

that LSB first

or MSB first

mode is set

correctly,

regardless of

shift mode.

To control

this register,

all channel

index bits in

Register 0x05

must be set.

0x01

Chip ID

(global)

8-bit chip ID, Bits[7:0]

AD6657A = 0x7B (default)

0x7B

Read only.

Channel Index and Transfer Registers

0x05

Channel

index

Enable

output

port for

Channel C

and

Channel D

Enable

output

port for

Channel A

and

Channel B

Open

Open

Channel D

enable

Channel C

enable

Channel B

enable

Channel A

enable

0xCF

Bits are set to

determine

which

channel on

the chip

receives the

next write

command;

applies to

local

registers.

0xFF

Transfer

Open

Open

Open

Open

Open

Open

Open

SW

transfer

1 = on

0 = off

(default)

0x00

Synchro-

nously

transfers

data from

the master

shift register

to the slave.

ADC Function Registers

0x08

Power modes

Open

Open

External

power-

down pin

function

(global)

0 = full

power-

down

1 =

standby

Open

Open

Open

Internal power-down

mode (local)

00 = normal operation

(default)

01 = full power-down

10 = standby

0x00

Determines

generic

modes of

chip opera-

tion.

0x0B

Clock divide

(global)

Open

Open

Clock divide phase

000 = 0 input clock cycles delayed

001 = 1 input clock cycle delayed

010 = 2 input clock cycles delayed

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

0x0C

Shuffle mode

(local)

Open

Open

Open

Open

Open

Open

Shuffle mode enable

00 = shuffle disabled

01 = shuffle enabled

0x01

Enables or

disables

shuffle

mode.

Rev. A | Page 31 of 36