AD6657ABBCZ datasheet(14/37 Pages) AD

14 / 37 page

Data Sheet

AD6657A

Pin No.

Mnemonic

Type

Description

D5+AB

Output

Channel A and Channel B LVDS Output Data 5—True.

D5−AB

Output

Channel A and Channel B LVDS Output Data 5—Complement.

K10

D6+AB

Output

Channel A and Channel B LVDS Output Data 6—True.

J10

D6−AB

Output

Channel A and Channel B LVDS Output Data 6—Complement.

M10

D7+AB

Output

Channel A and Channel B LVDS Output Data 7—True.

L10

D7−AB

Output

Channel A and Channel B LVDS Output Data 7—Complement.

K11

D8+AB

Output

Channel A and Channel B LVDS Output Data 8—True.

J11

D8−AB

Output

Channel A and Channel B LVDS Output Data 8—Complement.

M11

D9+AB

Output

Channel A and Channel B LVDS Output Data 9—True.

L11

D9−AB

Output

Channel A and Channel B LVDS Output Data 9—Complement.

K12

D10+AB

Output

Channel A and Channel B LVDS Output Data 10—True.

J12

D10−AB

Output

Channel A and Channel B LVDS Output Data 10—Complement.

M12

DCO+AB

Output

Data Clock LVDS Output for Channel A and Channel B—True.

L12

DCO−AB

Output

Data Clock LVDS Output for Channel A and Channel B—Complement.

D0+CD

Output

Channel C and Channel D LVDS Output Data 0—True.

D0−CD

Output

Channel C and Channel D LVDS Output Data 0—Complement.

D1+CD

Output

Channel C and Channel D LVDS Output Data 1—True.

D1−CD

Output

Channel C and Channel D LVDS Output Data 1—Complement.

D2+CD

Output

Channel C and Channel D LVDS Output Data 2—True.

D2−CD

Output

Channel C and Channel D LVDS Output Data 2—Complement.

D3+CD

Output

Channel C and Channel D LVDS Output Data 3—True.

D3−CD

Output

Channel C and Channel D LVDS Output Data 3—Complement.

D4+CD

Output

Channel C and Channel D LVDS Output Data 4—True.

D4−CD

Output

Channel C and Channel D LVDS Output Data 4—Complement.

D5+CD

Output

Channel C and Channel D LVDS Output Data 5—True.

D5−CD

Output

Channel C and Channel D LVDS Output Data 5—Complement.

D6+CD

Output

Channel C and Channel D LVDS Output Data 6—True.

D6−CD

Output

Channel C and Channel D LVDS Output Data 6—Complement.

D7+CD

Output

Channel C and Channel D LVDS Output Data 7—True.

D7−CD

Output

Channel C and Channel D LVDS Output Data 7—Complement.

D8+CD

Output

Channel C and Channel D LVDS Output Data 8—True.

D8−CD

Output

Channel C and Channel D LVDS Output Data 8—Complement.

D9+CD

Output

Channel C and Channel D LVDS Output Data 9—True.

D9−CD

Output

Channel C and Channel D LVDS Output Data 9—Complement.

D10+CD

Output

Channel C and Channel D LVDS Output Data 10—True.

D10−CD

Output

Channel C and Channel D LVDS Output Data 10—Complement.

DCO+CD

Output

Data Clock LVDS Output for Channel C and Channel D—True.

DCO−CD

Output

Data Clock LVDS Output for Channel C and Channel D—Complement.

MODE

Input

Mode Select Pin. Logic low enables NSR; logic high disables NSR.

SYNC

Input

Digital Synchronization Pin.

PDWN

Input

Power-Down Input (Active High).

SCLK

Input

SPI Clock.

SDIO

Input/Output

SPI Data.

CSB

Input

SPI Chip Select (Active Low).

Rev. A | Page 13 of 36

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