AD6657ABBCZ datasheet(20/37 Pages) AD

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Data Sheet

AD6657A

THEORY OF OPERATION

ADC ARCHITECTURE

The AD6657A architecture consists of a quad front-end sample-

and-hold circuit, followed by a pipelined, switched capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result in the digital correction logic. Alternately,

the 14-bit result can be processed through the NSR block before

it is sent to the digital correction logic.

The pipelined architecture permits the first stage to operate on

a new input sample and the remaining stages to operate on the

preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The residue amplifier magnifies the difference between

the reconstructed DAC output and the flash input for the next

stage in the pipeline. One bit of redundancy is used in each stage

to facilitate digital correction of flash errors. The last stage

simply consists of a flash ADC.

The input stage of each channel contains a differential sampling

circuit that can be ac- or dc-coupled in differential or single-ended

modes. The output staging block aligns the data, corrects errors,

and passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing adjustment of the output

drive current. During power-down, the output buffers go into a

high impedance state.

The AD6657A quad IF receiver can simultaneously digitize four

channels, making it ideal for diversity reception and digital pre-

distortion (DPD) observation paths in telecommunication systems.

Synchronization capability is provided to allow synchronized

timing between multiple channels or multiple devices.

Programming and control of the AD6657A are accomplished

using a 3-wire SPI-compatible serial interface.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6657A is a differential switched

capacitor circuit that has been designed for optimum perfor-

mance while processing a differential input signal.

The clock signal alternatively switches the input between sample

mode and hold mode (see Figure 35). When the input is switched

to sample mode, the signal source must be capable of charging

the sample capacitors and settling within 1/2 of a clock cycle.

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

In intermediate frequency (IF) undersampling applications,

any shunt capacitors should be reduced. In combination with

the driving source impedance, the shunt capacitors limit the

input bandwidth. For more information on this subject, see the

AN-742 Application Note, Frequency Domain Response of

Switched-Capacitor ADCs; AN-827 Application Note, A Resonant

Approach to Interfacing Amplifiers to Switched-Capacitor ADCs;

and the Analog Dialogue article, “Transformer-Coupled Front-End

for Wideband A/D Converters” (see www.analog.com).

Figure 35. Switched Capacitor Input

For best dynamic performance, match the source impedances

driving the VIN+ and VIN− pins.

An internal differential reference buffer creates positive and

negative reference voltages that define the input span of the ADC

core. The span of the ADC core is set by this buffer to 2 × VREF.

Input Common Mode

The analog inputs of the AD6657A are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. An on-board common-mode voltage reference is

included in the design and is available from the VCMx pins.

Optimum performance is achieved when the common-mode

voltage of the analog input is set by the VCMx pin voltage

(typically 0.5 × AVDD). The VCMx pins must be decoupled

to ground by a 0.1 µF capacitor.

CPAR1

CPAR2

CFB

BIAS

VIN+

VIN–

Rev. A | Page 19 of 36

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