WM8768

Production Data

w

PD Rev 4.1 March 2005

8

MASTER CLOCK TIMING

MCLK

t

MCLKL

t

MCLKH

t

MCLKY

Figure 1 DAC Master Clock Timing Requirements

Test Conditions

otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width

high

11

ns

MCLK System clock pulse width

low

11

ns

MCLK System clock cycle time

28

1000

ns

MCLK Duty cycle

40:60

60:40

Power-saving mode activated

After MCLK stopped

2

10

Us

Normal mode resumed

After MCLK re-started

0.5

1

MCLK

cycle

Table 1 Master Clock Timing Requirements

Note:

If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with

internal digital audio filters being reset.

In this power-saving mode, all registers will retain their values and can be

accessed in the normal manner through the control interface.

Once MCLK is restored, the DACs are automatically

powered up, but a write to the volume update register bit is required to restore the correct volume settings.

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

DIN1/2/3/4

LRCLK

WM8768

DAC

DSP/

DECODER

4

Figure 2 Audio Interface - Master Mode