WM8768

Production Data

w

PD Rev 4.1 March 2005

18

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8768 on the rising edge of BCLK

preceding a LRCLK transition. LRCLK are high during the left samples and low during the right

samples (Figure 14).

Figure 14 Right Justified Mode Timing Diagram

I2S MODE

In I

following a LRCLK transition. LRCLK are low during the left samples and high during the right

samples.

Figure 15 I

DSP MODE A

In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8768 on the second

rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4

data follow DAC channel 1 left data (Figure 16).

Figure 16 DSP Mode A Timing Diagram – DAC data input

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN1/2/3/4

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN1/2/3/4

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCKIN

1 BCKIN

1 BCKIN

LRCIN

BCKIN

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n

2

1

n-1

LSB

MSB

n

2

1

n-1

CHANNEL 1

RIGHT

2

1

CHANNEL 2

LEFT

n

n-1

CHANNEL 4

RIGHT

NO VALID DATA

1 BCKIN