WM8768

Production Data

w

PD Rev 4.1 March 2005

22

By default, LRCLK and DIN1/2/3/4 are sampled on the rising edge of BCLK and should ideally

change on the falling edge. Data sources that change LRCLK and DIN1/2/3/4 on the rising edge of

BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK

to the inverse of that shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

3

BCP

0

BCLK Polarity

0 : normal BCLK polarity

1: inverted BCLK polarity

The IWL[1:0] bits are used to control the input word length.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

5:4

IWL

[1:0]

00

Input Word Length

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: If 32-bit mode is selected in right justified mode, the WM8768 defaults to 24 bits.

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8768 pads the unused LSBs with zeros. If

the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bit I

minimum of 24 BCLKs and low for a minimum of 24 BCLKs. If exactly 32 bit clocks occur in one

left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.

A number of options are available to control how data from the Digital Audio Interface is applied to

the DAC channels.

DAC OUTPUT PHASE

The DAC phase control word determines whether the output of each DAC is non-inverted or inverted

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Bit

DAC

Phase

0

DAC1L/R

1 = invert

1

DAC2L/R

1 = invert

0000011

DAC Phase

8:6

PHASE

[2:0]

000

2

DAC3L/R

1 = invert

0001111

DAC4 Control

3

PHASE4

0

N/A

DAC4L/R

1 = invert

DIGITAL ZERO CROSS-DETECT

The digital volume control also incorporates a zero cross detect circuit which detects a transition

through the zero point before updating the digital volume control with the new volume. This is

enabled by control bit DZCEN.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

DAC Control

0

DZCEN

0

DAC Digital Volume Zero Cross

Enable:

0: Zero cross detect enabled

1: Zero cross detect disabled