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SSM2518CPZ-R7 数据表(PDF) 15 Page - Analog Devices

部件名 SSM2518CPZ-R7
功能描述  Digital Input Stereo, 2 W, Class-D Audio Power Amplifier
PDF  48 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM2518CPZ-R7 数据表(HTML) 15 Page - Analog Devices

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Datasheet
SSM2518
Rev. B | Page 15 of 48
MCLK pin to serve as the internal bit clock as well. In this case,
tie the BCLK pin to ground.
Once the SSM2518 has entered its power-down state, it is
possible to gate the clocks to conserve system power. However, a
valid master clock must be present for the audio amplifier to
operate. It is best to use a low jitter clock (less than 1 ns peak-
to-peak) to ensure the specified audio performance.



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