SSM2518CPZ-R7 datasheet(25/48 Pages) AD

25 / 48 page

Datasheet

SSM2518

Rev. B | Page 25 of 48

Table 12. REG_MAP Register Summary

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x00 Reset_Power_Control

[7:0] S_RST

RESERVED

NO_BCLK

MCS

SPWDN

0x05 RW

0x01 Edge_Clock_Control

[7:0] RESERVED

EDGE

ASR

0x00 RW

0x02 Serial_Interface_Sample_Rate_Control

[7:0] RESERVED SDATA_FMT

SAI

0x02 RW

0x03 Serial_Interface_Control

[7:0] BCLK_GEN LRCLK_MODE LRCLK_POL SAI_MSB

SLOT_WIDTH

BCLK_EDGE RESERVED

0x00 RW

0x04 Channel_Mapping_Control

[7:0] CH_SEL_R

CH_SEL_L

0x10 RW

0x05 Left_Volume_Control

[7:0] L_VOL

0x40 RW

0x06 Right_Volume_Control

[7:0] R_VOL

0x40 RW

0x07 Volume_Mute_Control

[7:0] AMUTE

RESERVED

ANA_GAIN DEEMP_EN VOL_LINK R_MUTE L_MUTE

M_MUTE

0x81 RW

0x08 Fault_Control_1

[7:0] OC_L

OC_R

MRCV

MAX_AR

ARCV

0x0C RW

0x09 Power_Fault_Control

[7:0] AR_TIME

RESERVED

AMP_LPM DAC_LPM R_PWDN L_PWDN

APWDN_EN 0x99 RW

0x0A DRC_Control_1

[7:0] RESERVED PRE_VOL

LIM_EN

COMP_EN EXP_EN

NG_EN

DRC_EN

0x7C RW

0x0B DRC_Control_2

[7:0] PEAK_ATT

PEAK_REL

0x5B RW

0x0C DRC_Control_3

[7:0] DRC_LT

DRC_CT

0x57 RW

0x0D DRC_Control_4

[7:0] DRC_ET

DRC_NT

0x89 RW

0x0E DRC_Control_5

[7:0] DRC_SMAX

DRC_SMIN

0x8C RW

0x0F DRC_Control_6

[7:0] DRC_ATT

DRC_DEC

0x77 RW

0x10 DRC_Control_7

[7:0] HDT_NOR

HDT_NG

0x26 RW

0x11 DRC_Control_8

[7:0] RESERVED

DRC_POST_G

RESERVED

0x1C RW

0x12 DRC_Control_9

[7:0] RESERVED

RMS_TAV

0x07 RW

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