FUSB302MPX. datasheet(10/35 Pages) ONSEMI

10 / 35 page

www.fairchildsemi.com

FUSB302

• Rev. 2

www.onsemi.com

Figure 12.

USB BMC Power Delivery Blocks

Power Level Determination

The

Type-C

specification

outlines

the

order

precedence for power level determination which covers

power levels from basic USB2.0 levels to the highest

levels of USB PD. The host software is expected to

follow the USB Type-C specification for charging current

priority based on feedback from the FUSB302 detection,

external BC1.2 detection and any USB Power Delivery

communication.

The FUSB302 does not integrate BC1.2 charger

detection which is assumed available in the USB

transceiver or USB charger in the system.

Power Up, Initialization and Reset

When power is first applied through VDD, the FUSB302

is reset and registers are initialized to the default values

shown in the register map.

The FUSB302 can be reset through software by

programming the SW_RES bit in the RESET register.

If no power applied to VDD then the SRC can recognize

the FUSB302 as a SNK.

PD Automatic Receive GoodCRC

The power delivery packets require a GoodCRC

acknowledge packet to be sent for each received packet

where the calculated CRC is the correct value. This

calculation is done by the FUSB302 and triggers the

I_CRC_CHK interrupt if the CRC is good. If the

AUTO_CRC

(Switches1

bit)

set

and

AUTO_PRE=0, then the FUSB302 will automatically

send the GoodCRC control packet in response to

alleviate the local processor from responding quickly to

the received packet. If GoodCRC is required for

anything beyond SOP, then enable SOP*.

PD Send

The FUSB302 implements part of the PD protocol layer

for sending packets in an autonomous fashion.

PD Automatic Sending Retries

If GoodCRC packet is not received and AUTO_RETRY

is set, then a retry of the same message that was in the

TxFIFO written by the processor is executed within

tRetry and that is repeated for NRETRY times.

PD Send Soft Reset

If the correct GoodCRC packet is still not received for all

retries then I_RETRYFAIL interrupt is triggered and if

AUTO_SOFT_RESET is set, then a Soft Reset packet

is created (MessageID is set to 0 and the processor

upon servicing I_RETRYFAIL would set the true

MessageIDCounter to 0.

If this Soft Reset is sent successfully where a GoodCRC

control packet is received with a MessageID=0 then

I_TXSENT interrupt occurs.

If not, this Soft Reset packet is retried NRETRIES times

(MessageID is always 0 for all retries) if a GoodCRC

acknowledge

packet

not

received

with

CRCReceiveTimer expiring (tReceive of 1.1 ms max). If

all retries fail, then I_SOFTFAIL interrupt is triggered.

PD Send Hard Reset

If all retries of the soft reset packet fail and if

AUTO_HARD_RESET is set, then a hard reset ordered

set is sent by loading up the TxFIFO with RESET1,

RESET1, RESET1, RESET2 and sending a hard reset.

Note only one hard reset is sent since the typical retry

mech

anism doesn’t apply. The processor’s policy

engine firmware is responsible for retrying the hard

reset is it doesn’t receive the required response.

FIFO

Code/

Control

Logic

CDR

CRC32

4B5B

BMC

CC1

CC2

Hard

Reset

Soft Reset

Automatic

Sending Retries

PD Packet

Sent

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