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FUSB302

• Rev. 2

11

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requirements. This block is designed for Fast Mode Plus

traffic up to 1 MHz SCL operation.

The TOGGLE features allow for very low power operation

with slow clocking thus may not be fully compliant to the

sequence are shown in Figure 13 and Figure 14

respectively.

Figure 13.

Figure 14.

S

WR A

A

A

A

A

A P

Note:

Single Byte read is initiated by Master with P immediately following first data byte

8bits

8bits

8bits

Write Data K+2

Slave Address

Register Address K

Write Data

Write Data K+1

Write Data K+N-1

S

WR A

A S

RD A

A

A

NA P

Register address to Read specified

Note:

8bits

If Register is not specified Master will begin read from current register. In this case only sequence showing in Red

bracket is needed

Single or multi byte read executed from current register location (Single Byte read is

initiated by Master with NA immediately following first data byte)

Read Data K+1

Read Data K+N-1

8bits

8bits

8bits

Slave Address

Register Address K

Read Data K

Slave Address

From Master to Slave

S

Start Condition

NA NOT Acknowledge (SDA High)

RD

Read =1

From Slave to Master

A

Acknowledge (SDA Low)

WR Write=0

P

Stop Condition